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GICD_IGROUPR<n>E

GICD_IGROUPR<n>E, Interrupt Group Registers (extended SPI range), n = 0 - 31

The GICD_IGROUPR<n>E characteristics are:

Purpose

Controls whether the corresponding SPI in the extended SPI range is in Group 0 or Group 1.

Configuration

This register is present only when GICv3.1 is implemented. Otherwise, direct accesses to GICD_IGROUPR<n>E are RES0.

When GICD_TYPER.ESPI==0, these registers are RES0.

When GICD_TYPER.ESPI==1:

The number of implemented GICD_IGROUPR<n>E registers is (GICD_TYPER.ESPI_range+1). Registers are numbered from 0.
When GICD_CTLR.DS==0, this register is Secure.

Attributes

GICD_IGROUPR<n>E is a 32-bit register.

Field descriptions

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Group_status_bit31	Group_status_bit30	Group_status_bit29	Group_status_bit28	Group_status_bit27	Group_status_bit26	Group_status_bit25	Group_status_bit24	Group_status_bit23	Group_status_bit22	Group_status_bit21	Group_status_bit20	Group_status_bit19	Group_status_bit18	Group_status_bit17	Group_status_bit16	Group_status_bit15	Group_status_bit14	Group_status_bit13	Group_status_bit12	Group_status_bit11	Group_status_bit10	Group_status_bit9	Group_status_bit8	Group_status_bit7	Group_status_bit6	Group_status_bit5	Group_status_bit4	Group_status_bit3	Group_status_bit2	Group_status_bit1	Group_status_bit0

Group_status_bit<x>, bit [x], for x = 31 to 0

Group status bit.

Group_status_bit<x>	Meaning
0b0	When GICD_CTLR.DS==1, the corresponding interrupt is Group 0. When GICD_CTLR.DS==0, the corresponding interrupt is Secure.
0b1	When GICD_CTLR.DS==1, the corresponding interrupt is Group 1. When GICD_CTLR.DS==0, the corresponding interrupt is Non-secure Group 1.

Group_status_bit<x>

Meaning

0b0

When GICD_CTLR.DS==1, the corresponding interrupt is Group 0.

When GICD_CTLR.DS==0, the corresponding interrupt is Secure.

0b1

When GICD_CTLR.DS==1, the corresponding interrupt is Group 1.

When GICD_CTLR.DS==0, the corresponding interrupt is Non-secure Group 1.

If affinity routing is enabled for the Security state of an interrupt, the bit that corresponds to the interrupt is concatenated with the equivalent bit in GICD_IGRPMODR<n>E to form a 2-bit field that defines an interrupt group. The encoding of this field is described in GICD_IGRPMODR<n>E.

If affinity routing is disabled for the Security state of an interrupt, the bit is RES0:

The reset behavior of this field is:

On a GIC reset, this field resets to '0'.

Additional information

For INTID m, when DIV and MOD are the integer division and modulo operations:

The corresponding GICD_IGROUPR<n>E number, n, is given by n = (m-4096) DIV 32.
The offset of the required GICD_IGROUPR<n>E is (0x1000 + (4*n)).
The bit number of the required group modifier bit in this register is (m-4096) MOD 32.

Accessing GICD_IGROUPR<n>E

When affinity routing is not enabled for the Security state of an interrupt in GICD_IGROUPR<n>E, the corresponding bit is RES0.

When GICD_CTLR.DS==0, bits corresponding to Secure SPIs are RAZ/WI to Non-secure accesses.

Bits corresponding to unimplemented interrupts are RAZ/WI.

GICD_IGROUPR<n>E can be accessed through the memory-mapped interfaces:

Component	Frame	Offset	Instance
GIC Distributor	Dist_base	0x1000 + (4 * n)	GICD_IGROUPR<n>E

Accesses to this register are RW.

2026-03-12 12:23:09, 2025-09_rel_asl1