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GICD_INMIR<n>E

GICD_INMIR<n>E, Non-maskable Interrupt Registers for Extended SPIs, x = 0 to 31, n = 0 - 31

The GICD_INMIR<n>E characteristics are:

Purpose

Holds whether the corresponding SPI in the extended SPI range has the non-maskable property.

Configuration

This register is present only when GICv3.1 is implemented and GICD_TYPER.NMI == 1. Otherwise, direct accesses to GICD_INMIR<n>E are RES0.

When GICD_TYPER.ESPI is 0, these registers are RES0.

When GICD_TYPER.ESPI is 1: the number of implemented GICD_INMIR<n>E registers is (GICD_TYPER.ESPI_range+1). Registers are numbered from 0.

Attributes

GICD_INMIR<n>E is a 32-bit register.

Field descriptions

313029282726252423222120191817161514131211109876543210
NMI31NMI30NMI29NMI28NMI27NMI26NMI25NMI24NMI23NMI22NMI21NMI20NMI19NMI18NMI17NMI16NMI15NMI14NMI13NMI12NMI11NMI10NMI9NMI8NMI7NMI6NMI5NMI4NMI3NMI2NMI1NMI0

NMI<x>, bit [x], for x = 31 to 0

Non-maskable property.

NMI<x>Meaning
0b0

Interrupt does not have the non-maskable property.

0b1

Interrupt has the non-maskable property.

If affinity routing is disabled for the Security state of an interrupt, the bit is RES0.

This bit is RES0 when the corresponding interrupt is configured as Group 0.

The reset behavior of this field is:

Additional information

For INTID m, when DIV and MOD are the integer division and modulo operations:

Accessing GICD_INMIR<n>E

When affinity routing is not enabled for the Security state of an interrupt in GICD_IGROUPR<n>E, the corresponding bit is RES0.

Bits corresponding to unimplemented interrupts are RAZ/WI.

When GICD_CTLR.DS==0, bits corresponding to Group 0 and Secure Group 1 interrupts are RAZ/WI to Non-secure accesses.

Note

Implementations must ensure that an interrupt that is pending at the time of the write uses either the old value or the new value and must ensure that the interrupt is neither lost nor handled more than one time. The effect of the change must be visible in finite time.

GICD_INMIR<n>E can be accessed through the memory-mapped interfaces:

ComponentFrameOffsetInstance
GIC DistributorDist_base0x3B00 + (4 * n)GICD_INMIR<n>E

Accesses to this register are RW.


2026-03-12 12:23:09, 2025-09_rel_asl1

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