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MPAMF_SIDR

MPAMF_SIDR, MPAM Features Secure Identification Register

The MPAMF_SIDR characteristics are:

Purpose

The MPAMF_SIDR is a 32-bit read-only register that indicates the maximum Secure PARTID and Secure PMG on this MSC.

Configuration

The power domain of MPAMF_SIDR is IMPLEMENTATION DEFINED.

This register is present only when FEAT_MPAMv0p1 is implemented or FEAT_MPAMv1p0 is implemented. Otherwise, direct accesses to MPAMF_SIDR are RES0.

The power and reset domain of each MSC component is specific to that component.

Attributes

MPAMF_SIDR is a 32-bit register.

Field descriptions

313029282726252423222120191817161514131211109876543210
RES0S_PMG_MAXS_PARTID_MAX

Bits [31:24]

Reserved, RES0.

S_PMG_MAX, bits [23:16]

Maximum value of Secure PMG supported by this component.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

S_PARTID_MAX, bits [15:0]

Maximum value of Secure PARTID supported by this component.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

Accessing MPAMF_SIDR

This register is only within the Secure MPAM feature page memory frame.

MPAMF_SIDR must only be readable from the Secure MPAM feature page. If the system or the MSC does not support the Secure address map, this register must not be accessible.

MPAMF_SIDR can be accessed through the memory-mapped interfaces:

ComponentFrameOffsetInstance
MPAMMPAMF_BASE_s0x0008MPAMF_SIDR_s

Accesses to this register are RO.


2026-03-12 12:23:09, 2025-09_rel_asl1

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