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MSMON_CSA

MSMON_CSA, MPAM Cache Storage Allocation Monitor Register

The MSMON_CSA characteristics are:

Purpose

Accesses the cache storage allocation monitor instance selected by MSMON_CFG_MON_SEL.

Configuration

The power domain of MSMON_CSA is IMPLEMENTATION DEFINED.

This register is present only when (FEAT_MPAMv0p1 is implemented or FEAT_MPAMv1p0 is implemented), MPAMF_IDR.HAS_MSMON == 1, and MPAMF_MSMON_IDR.MSMON_CSA == 1. Otherwise, direct accesses to MSMON_CSA are RES0.

If FEAT_MPAM is implemented, the following statements apply:

If any one of these features is implemented:

then, the following statements apply:

The power and reset domain of each MSC component is specific to that component.

Attributes

MSMON_CSA is a 32-bit register.

Field descriptions

313029282726252423222120191817161514131211109876543210
NRDYVALUE

NRDY, bit [31]

Not Ready. Indicates whether the monitor has possibly inaccurate data.

NRDYMeaning
0b0

The monitor instance is ready and the MSMON_CSA.VALUE field is accurate.

0b1

The monitor instance is not ready and the contents of the MSMON_CSA.VALUE field might be inaccurate or otherwise not represent the actual cache storage allocations.

VALUE, bits [30:0]

Cache storage allocation counter value if MSMON_CSA.NRDY is 0. Invalid if MSMON_CSA.NRDY is 1.

VALUE is the scaled count of bytes allocated since the monitor was last reset that met the criteria set in MSMON_CFG_CSA_FLT and MSMON_CFG_CSA_CTL for the monitor instance selected by MSMON_CFG_MON_SEL.

If MSMON_CFG_CSA_CTL.SCLEN enables scaling, the count in VALUE is the number of bytes shifted right by MPAMF_CSAMON_IDR.SCALE bit positions and rounded.

Accessing MSMON_CSA

This register is within the MPAM feature page memory frames.

If FEAT_MPAM is implemented, the following statements apply:

If both FEAT_MPAM and FEAT_RME are implemented, the following statements apply:

If any one of these features is implemented:

then, the following statements apply:

Otherwise, the following statements apply:

MSMON_CSA can be accessed through the memory-mapped interfaces:

ComponentFrameOffsetInstance
MPAMMPAMF_BASE_s0x08A0MSMON_CSA_s

Accesses to this register are RW.

ComponentFrameOffsetInstance
MPAMMPAMF_BASE_ns0x08A0MSMON_CSA_ns

Accesses to this register are RW.

ComponentFrameOffsetInstance
MPAMMPAMF_BASE_rt0x08A0MSMON_CSA_rt

When FEAT_RME is implemented, accesses to this register are RW.

ComponentFrameOffsetInstance
MPAMMPAMF_BASE_rl0x08A0MSMON_CSA_rl

When FEAT_RME is implemented, accesses to this register are RW.


2026-03-12 12:23:09, 2025-09_rel_asl1

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