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TRBPIDR5, Peripheral Identification Register 5

The TRBPIDR5 characteristics are:

Purpose

Provides discovery information about the component.

For additional information, see the CoreSight Architecture Specification.

Configuration

TRBPIDR5 is in the Core power domain.

This register is present only when FEAT_TRBE_EXT is implemented. Otherwise, direct accesses to TRBPIDR5 are RES0.

Attributes

TRBPIDR5 is a 32-bit register.

Field descriptions

Bits [31:0]

Accessing TRBPIDR5

TRBPIDR5 can be accessed through the external debug interface:

Accessible as follows:

• When DoubleLockStatus() or !IsCorePowered(), accesses to this register generate an error response.
• Otherwise, accesses to this register are RO.

2026-03-12 12:23:09, 2025-09_rel_asl1

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