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PMPIDR2
AArch32 Registers
AArch64 Registers
AArch32 Instructions
AArch64 Instructions
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External Registers
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Proprietary Notice

PMPIDR2, Performance Monitors Peripheral Identification Register 2

The PMPIDR2 characteristics are:

Purpose

Provides information to identify a Performance Monitor component.

For more information, see 'About the Peripheral identification scheme'.

Configuration

This register is present only when FEAT_PMUv3_EXT is implemented and an implementation implements PMPIDR2. Otherwise, direct accesses to PMPIDR2 are RES0.

If FEAT_DoPD is implemented, this register is in the Core power domain. If FEAT_DoPD is not implemented, this register is in the Debug power domain.

This register is required for CoreSight compliance.

Attributes

PMPIDR2 is a 32-bit register.

This register is part of the PMU block.

Field descriptions

313029282726252423222120191817161514131211109876543210
RES0REVISIONJEDECDES_1

Bits [31:8]

Reserved, RES0.

REVISION, bits [7:4]

Part major revision. Parts can also use this field to extend Part number to 16-bits.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

JEDEC, bit [3]

Indicates a JEP106 identity code is used.

Reads as 0b1.

Access to this field is RO.

DES_1, bits [2:0]

Designer, most significant bits of JEP106 ID code. For Arm Limited, this field is 0b011.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

Accessing PMPIDR2

Accesses to this register use the following encodings:

Accessible at offset 0xFE8 from PMU

AArch32 Registers
AArch64 Registers
AArch32 Instructions
AArch64 Instructions
Index by Encoding
External Registers
External Registers by Offset
Registers by Functional Group
Proprietary Notice

2026-03-12 12:23:09, 2025-09_rel_asl1

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