AMAIR1 Auxiliary Memory Attribute Indirection Register 1 when FEAT_AA32EL1 is implemented AMAIR_EL1 Architectural AArch64 31 0 63 32 31 0 63 32 When using the Long-descriptor format translation tables for stage 1 translations, provides IMPLEMENTATION DEFINED memory attributes for the memory regions specified by MAIR1. IMP DEF Memory When EL3 is using AArch32, write access to AMAIR1(S) is disabled when the CP15SDISABLE signal is asserted HIGH. This register is banked between AMAIR1 and AMAIR1_S and AMAIR1_NS. AMAIR1 is a 32-bit register. This register has the following instances: AMAIR1, when EL3 is not implemented or FEAT_AA64 is implemented. AMAIR1_S, when FEAT_AA32EL3 is implemented. AMAIR1_NS, when FEAT_AA32EL3 is implemented. This register is RES0 in the following cases: When an implementation does not provide any IMPLEMENTATION DEFINED memory attributes. When the Long-descriptor translation table format is not used. If EL3 is implemented and is using AArch32: AMAIR1(S) gives the value for memory accesses from Secure state. AMAIR1(NS) gives the value for memory accesses from Non-secure states other than Hyp mode. Any IMPLEMENTATION DEFINED memory attributes are additional qualifiers for the memory locations and must not change the architected behavior specified by MAIR0 and MAIR1. In a typical implementation, AMAIR0 and AMAIR1 split into eight one-byte fields, corresponding to the MAIRn.Attr<n> fields, but the architecture does not require them to do so. IMPLEMENTATION DEFINED 31 0 31:0 IMPLEMENTATION DEFINED. AU MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>} if !IsFeatureImplemented(FEAT_AA32EL1) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T10 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T10 == '1' then AArch32_TakeHypTrapException(0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HCR_EL2().TRVM == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HCR().TRVM == '1' then AArch32_TakeHypTrapException(0x03); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) then R(t) = AMAIR1_NS(); else R(t) = AMAIR1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) then R(t) = AMAIR1_NS(); else R(t) = AMAIR1(); end; elsif PSTATE.EL == EL3 then if SCR().NS == '0' then R(t) = AMAIR1_S(); else R(t) = AMAIR1_NS(); end; end; MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>} if !IsFeatureImplemented(FEAT_AA32EL1) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T10 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T10 == '1' then AArch32_TakeHypTrapException(0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HCR_EL2().TVM == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HCR().TVM == '1' then AArch32_TakeHypTrapException(0x03); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) then AMAIR1_NS() = R(t); else AMAIR1() = R(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) then AMAIR1_NS() = R(t); else AMAIR1() = R(t); end; elsif PSTATE.EL == EL3 then if SCR().NS == '0' && CP15SDISABLE == HIGH then Undefined(); elsif SCR().NS == '0' && CP15SDISABLE2 == HIGH then Undefined(); else if SCR().NS == '0' then AMAIR1_S() = R(t); else AMAIR1_NS() = R(t); end; end; end; 2026-03-26 20:27:25 2026-03_rel