<?xml version='1.0' encoding='utf-8'?>
<!DOCTYPE register_page SYSTEM "registers.dtd">
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<register_page>
  <registers>
  
    <register execution_state="AArch32" is_register="True" is_internal="True" is_stub_entry="False">
      <reg_short_name>AMCGCR</reg_short_name>
        
        <reg_long_name>Activity Monitors Counter Group Configuration Register</reg_long_name>



      
            <reg_condition otherwise="UNDEFINED">when FEAT_AMUv1 is implemented and FEAT_AA32 is implemented</reg_condition>
      




          <reg_reset_value></reg_reset_value>

      <reg_mappings>
        



    
      
      <reg_mapping>
        
  

    

  

    <mapped_name filename="AArch64-amcgcr_el0.xml">AMCGCR_EL0</mapped_name>
  <mapped_type>Architectural</mapped_type>
      <mapped_execution_state>AArch64</mapped_execution_state>
    <mapped_from_startbit>31</mapped_from_startbit>
    <mapped_from_endbit>0</mapped_from_endbit>
    <mapped_to_startbit>31</mapped_to_startbit>
    <mapped_to_endbit>0</mapped_to_endbit>
    <mapped_from_rangeset output="31:0">
      <range>
        <msb>31</msb>
        <lsb>0</lsb>
      </range>
    </mapped_from_rangeset>
    <mapped_to_rangeset output="31:0">
      <range>
        <msb>31</msb>
        <lsb>0</lsb>
      </range>
    </mapped_to_rangeset>

      </reg_mapping>
    
      
      <reg_mapping>
        
  

    

  

    <mapped_name filename="amu.amcgcr.xml">AMCGCR</mapped_name>
  <mapped_type>Architectural</mapped_type>
    <mapped_execution_state>External</mapped_execution_state>
    <mapped_from_startbit>31</mapped_from_startbit>
    <mapped_from_endbit>0</mapped_from_endbit>
    <mapped_to_startbit>31</mapped_to_startbit>
    <mapped_to_endbit>0</mapped_to_endbit>
    <mapped_from_rangeset output="31:0">
      <range>
        <msb>31</msb>
        <lsb>0</lsb>
      </range>
    </mapped_from_rangeset>
    <mapped_to_rangeset output="31:0">
      <range>
        <msb>31</msb>
        <lsb>0</lsb>
      </range>
    </mapped_to_rangeset>

      </reg_mapping>

      </reg_mappings>

        <reg_purpose>
          
    
      <purpose_text>
        <para>Provides information on the number of activity monitor event counters implemented within each counter group.</para>
      </purpose_text>

        </reg_purpose>

      <reg_groups>
          <reg_group>AMU</reg_group>
      </reg_groups>
      
      
        
      <reg_attributes>
          
    
      <attributes_text>
        <para>AMCGCR is a 32-bit register.</para>
      </attributes_text>

      </reg_attributes>
      <reg_fieldsets>
        






<fields id="fieldset_0" length="32">
  <text_before_fields/>
  <field id="fieldset_0-31_16" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False" rwtype="RES0">
    <field_msb>31</field_msb>
    <field_lsb>16</field_lsb>
    <rel_range>31:16</rel_range>
    <field_description order="before"/>
    <field_description order="before">
      <para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para>
    </field_description>
  </field>
  <field id="fieldset_0-15_8" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="True" is_partial_field="False" is_conditional_field_name="False">
    <field_name>CG1NC</field_name>
    <field_msb>15</field_msb>
    <field_lsb>8</field_lsb>
    <rel_range>15:8</rel_range>
    <field_description order="before"><para>Counter Group 1 Number of Counters. Highest index of the implemented counters in the auxiliary counter group, plus one. Zero indicates that there are no counters in the auxiliary counter group.</para>
<para>In an implementation that includes <xref filename="A_armv8_architecture_extensions.fm" linkend="FEAT_AMUv1">FEAT_AMUv1</xref>, the permitted range of values is 0 to 16.</para>
<para>If FEAT_AMUv1p1 is implemented, then <register_link state="AArch64" id="AArch64-amcg1idr_el0.xml">AMCG1IDR_EL0</register_link> further defines which auxiliary counters are implemented, and the counters in the auxiliary counter group might be indexed non-contiguously.</para></field_description>
    <field_description order="after">
      <para>This field has an <arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word> value.</para>
    </field_description>
    <field_access>
      <field_access_state>
        <field_access_type>RO</field_access_type>
      </field_access_state>
    </field_access>
  </field>
  <field id="fieldset_0-7_0" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="True" is_partial_field="False" is_conditional_field_name="False">
    <field_name>CG0NC</field_name>
    <field_msb>7</field_msb>
    <field_lsb>0</field_lsb>
    <rel_range>7:0</rel_range>
    <field_description order="before">
      <para>Counter Group 0 Number of Counters. The number of counters in the architected counter group.</para>
    </field_description>
    <field_description order="after">
      <para>Reads as <hexnumber>0x04</hexnumber>.</para>
    </field_description>
    <field_access>
      <field_access_state>
        <field_access_type>RO</field_access_type>
      </field_access_state>
    </field_access>
  </field>
  <text_after_fields/>
</fields>




<reg_fieldset length="32">
  <fieldat id="fieldset_0-31_16" msb="31" lsb="16"/>
  <fieldat id="fieldset_0-15_8" msb="15" lsb="8"/>
  <fieldat id="fieldset_0-7_0" msb="7" lsb="0"/>
</reg_fieldset>


      </reg_fieldsets>

      <access_mechanisms>
          






    
        
        <access_mechanism accessor="MRC AMCGCR" type="SystemAccessor">
            <encoding>
            <access_instruction>MRC{&lt;c&gt;}{&lt;q&gt;} &lt;coproc&gt;, {#}&lt;opc1&gt;, &lt;Rt&gt;, &lt;CRn&gt;, &lt;CRm&gt;{, {#}&lt;opc2&gt;}</access_instruction>
                
                <enc n="coproc" v="0b1111"/>
                
                <enc n="opc1" v="0b000"/>
                
                <enc n="CRn" v="0b1101"/>
                
                <enc n="CRm" v="0b0010"/>
                
                <enc n="opc2" v="0b010"/>
            </encoding>
            <access_permission>
                <ps name="MRC" sections="1" secttype="access_permission">
                <pstext>
if !(IsFeatureImplemented(FEAT_AMUv1) &amp;&amp; IsFeatureImplemented(FEAT_AA32)) then
    Undefined();
elsif PSTATE.EL == EL0 then
    if HaveEL(EL3) &amp;&amp; EL3SDDUndefPriority() &amp;&amp; IsFeatureImplemented(FEAT_AA64EL3) &amp;&amp; !ELUsingAArch32(EL3) &amp;&amp; CPTR_EL3().TAM == '1' then
        Undefined();
    elsif IsFeatureImplemented(FEAT_AA64EL1) &amp;&amp; !ELUsingAArch32(EL1) &amp;&amp; AMUSERENR_EL0().EN == '0' then
        if EL2Enabled() &amp;&amp; (IsFeatureImplemented(FEAT_AA64EL2) &amp;&amp; !ELUsingAArch32(EL2)) &amp;&amp; HCR_EL2().TGE == '1' then
            AArch64_AArch32SystemAccessTrap(EL2, 0x03);
        else
            AArch64_AArch32SystemAccessTrap(EL1, 0x03);
        end;
    elsif IsFeatureImplemented(FEAT_AA32EL1) &amp;&amp; ELUsingAArch32(EL1) &amp;&amp; AMUSERENR().EN == '0' then
        if EL2Enabled() &amp;&amp; (IsFeatureImplemented(FEAT_AA64EL2) &amp;&amp; !ELUsingAArch32(EL2)) &amp;&amp; HCR_EL2().TGE == '1' then
            AArch64_AArch32SystemAccessTrap(EL2, 0x03);
        elsif EL2Enabled() &amp;&amp; (IsFeatureImplemented(FEAT_AA32EL2) &amp;&amp; ELUsingAArch32(EL2)) &amp;&amp; HCR().TGE == '1' then
            AArch32_TakeHypTrapException(0x00);
        else
            Undefined();
        end;
    elsif EL2Enabled() &amp;&amp; (IsFeatureImplemented(FEAT_AA64EL2) &amp;&amp; !ELUsingAArch32(EL2)) &amp;&amp; !ELIsInHost(EL0) &amp;&amp; HSTR_EL2().T13 == '1' then
        AArch64_AArch32SystemAccessTrap(EL2, 0x03);
    elsif EL2Enabled() &amp;&amp; (IsFeatureImplemented(FEAT_AA32EL2) &amp;&amp; ELUsingAArch32(EL2)) &amp;&amp; HSTR().T13 == '1' then
        AArch32_TakeHypTrapException(0x03);
    elsif EL2Enabled() &amp;&amp; (IsFeatureImplemented(FEAT_AA64EL2) &amp;&amp; !ELUsingAArch32(EL2)) &amp;&amp; CPTR_EL2().TAM == '1' then
        AArch64_AArch32SystemAccessTrap(EL2, 0x03);
    elsif EL2Enabled() &amp;&amp; (IsFeatureImplemented(FEAT_AA32EL2) &amp;&amp; ELUsingAArch32(EL2)) &amp;&amp; HCPTR().TAM == '1' then
        AArch32_TakeHypTrapException(0x03);
    elsif HaveEL(EL3) &amp;&amp; IsFeatureImplemented(FEAT_AA64EL3) &amp;&amp; !ELUsingAArch32(EL3) &amp;&amp; CPTR_EL3().TAM == '1' then
        if EL3SDDUndef() then
            Undefined();
        else
            AArch64_AArch32SystemAccessTrap(EL3, 0x03);
        end;
    else
        R(t) = AMCGCR();
    end;
elsif PSTATE.EL == EL1 then
    if HaveEL(EL3) &amp;&amp; EL3SDDUndefPriority() &amp;&amp; IsFeatureImplemented(FEAT_AA64EL3) &amp;&amp; !ELUsingAArch32(EL3) &amp;&amp; CPTR_EL3().TAM == '1' then
        Undefined();
    elsif EL2Enabled() &amp;&amp; IsFeatureImplemented(FEAT_AA64EL2) &amp;&amp; !ELUsingAArch32(EL2) &amp;&amp; HSTR_EL2().T13 == '1' then
        AArch64_AArch32SystemAccessTrap(EL2, 0x03);
    elsif EL2Enabled() &amp;&amp; IsFeatureImplemented(FEAT_AA32EL2) &amp;&amp; ELUsingAArch32(EL2) &amp;&amp; HSTR().T13 == '1' then
        AArch32_TakeHypTrapException(0x03);
    elsif EL2Enabled() &amp;&amp; IsFeatureImplemented(FEAT_AA64EL2) &amp;&amp; !ELUsingAArch32(EL2) &amp;&amp; CPTR_EL2().TAM == '1' then
        AArch64_AArch32SystemAccessTrap(EL2, 0x03);
    elsif EL2Enabled() &amp;&amp; IsFeatureImplemented(FEAT_AA32EL2) &amp;&amp; ELUsingAArch32(EL2) &amp;&amp; HCPTR().TAM == '1' then
        AArch32_TakeHypTrapException(0x03);
    elsif HaveEL(EL3) &amp;&amp; IsFeatureImplemented(FEAT_AA64EL3) &amp;&amp; !ELUsingAArch32(EL3) &amp;&amp; CPTR_EL3().TAM == '1' then
        if EL3SDDUndef() then
            Undefined();
        else
            AArch64_AArch32SystemAccessTrap(EL3, 0x03);
        end;
    else
        R(t) = AMCGCR();
    end;
elsif PSTATE.EL == EL2 then
    if HaveEL(EL3) &amp;&amp; EL3SDDUndefPriority() &amp;&amp; IsFeatureImplemented(FEAT_AA64EL3) &amp;&amp; !ELUsingAArch32(EL3) &amp;&amp; CPTR_EL3().TAM == '1' then
        Undefined();
    elsif HaveEL(EL3) &amp;&amp; IsFeatureImplemented(FEAT_AA64EL3) &amp;&amp; !ELUsingAArch32(EL3) &amp;&amp; CPTR_EL3().TAM == '1' then
        if EL3SDDUndef() then
            Undefined();
        else
            AArch64_AArch32SystemAccessTrap(EL3, 0x03);
        end;
    else
        R(t) = AMCGCR();
    end;
elsif PSTATE.EL == EL3 then
    R(t) = AMCGCR();
end;
                </pstext>
                </ps>
            </access_permission>
        </access_mechanism>

      </access_mechanisms>

      <arch_variants>
      </arch_variants>
  </register>
</registers>
<timestamp>2026-03-26 20:27:25</timestamp>
<commit_id>2026-03_rel</commit_id>
</register_page>