ATS12NSOPW Address Translate Stages 1 and 2 Non-secure Only PL1 Write when FEAT_AA32EL2 is implemented Performs stage 1 and 2 address translations as defined for PL1 and the Non-secure state, with permissions as if writing to the given virtual address. Address ATS12NSOPW is a 32-bit System instruction. IA Input address for translation 31 0 31:0 Input address for translation. The resulting address can be read from the PAR. This System instruction takes a VA as input. The resulting address is the PA that is the output address of the stage 2 translation. MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>} if !IsFeatureImplemented(FEAT_AA32EL2) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T7 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T7 == '1' then AArch32_TakeHypTrapException(0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && IsCurrentSecurityState(SS_Secure) then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && IsCurrentSecurityState(SS_Secure) then AArch64_AArch32SystemAccessTrap(EL3, 0x03); else Undefined(); end; elsif PSTATE.EL == EL2 then AArch32_AT(R(t), TranslationStage_12, EL1, ATAccess_Write); elsif PSTATE.EL == EL3 then AArch32_AT(R(t), TranslationStage_12, EL1, ATAccess_Write); end; 2026-03-26 20:27:25 2026-03_rel