<?xml version='1.0' encoding='utf-8'?>
<!DOCTYPE register_page SYSTEM "registers.dtd">
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<?xml-stylesheet href="one_register.xsl" type="text/xsl" ?>







<register_page>
  <registers>
  
    <register execution_state="AArch32" is_register="False" is_internal="True" is_stub_entry="False">
      <reg_short_name>BPIALL</reg_short_name>
        
        <reg_long_name>Branch Predictor Invalidate All</reg_long_name>



      
            <reg_condition otherwise="UNDEFINED">when FEAT_AA32EL1 is implemented</reg_condition>
      




          <reg_reset_value></reg_reset_value>

      <reg_mappings>
        




      </reg_mappings>

        <reg_purpose>
          
    
      <purpose_text>
        <para>Invalidate all entries from branch predictors.</para>
      </purpose_text>

        </reg_purpose>

      <reg_groups>
            <reg_group>Cache</reg_group>
      </reg_groups>
      <reg_configuration>
        
    
      <configuration_text>
        <para>In an implementation where the branch predictors are architecturally invisible, this instruction can execute as a NOP.</para>
      </configuration_text>

      </reg_configuration>
      
      
        
      <reg_attributes>
          
    
      <attributes_text>
        <para>BPIALL is a 32-bit System instruction.</para>
      </attributes_text>

      </reg_attributes>
      <reg_fieldsets>
        







      </reg_fieldsets>

      <access_mechanisms>
          


  
    
      <access_permission_text>
        <para>The PE ignores the value of &lt;Rt&gt;. Software does not have to write a value to this register before issuing this instruction.</para>

      </access_permission_text>
      <access_permission_text>
        <para>When <register_link state="AArch32" id="AArch32-hcr.xml">HCR</register_link>.FB is 1, at Non-secure EL1 this instruction executes as a <register_link state="AArch32" id="AArch32-bpiallis.xml">BPIALLIS</register_link>.</para>
      </access_permission_text>





    
        
        <access_mechanism accessor="MCR BPIALL" type="SystemAccessor">
            <encoding>
            <access_instruction>MCR{&lt;c&gt;}{&lt;q&gt;} &lt;coproc&gt;, {#}&lt;opc1&gt;, &lt;Rt&gt;, &lt;CRn&gt;, &lt;CRm&gt;{, {#}&lt;opc2&gt;}</access_instruction>
                
                <enc n="coproc" v="0b1111"/>
                
                <enc n="opc1" v="0b000"/>
                
                <enc n="CRn" v="0b0111"/>
                
                <enc n="CRm" v="0b0101"/>
                
                <enc n="opc2" v="0b110"/>
            </encoding>
            <access_permission>
                <ps name="MCR" sections="1" secttype="access_permission">
                <pstext>
if !IsFeatureImplemented(FEAT_AA32EL1) then
    Undefined();
elsif PSTATE.EL == EL0 then
    Undefined();
elsif PSTATE.EL == EL1 then
    if EL2Enabled() &amp;&amp; IsFeatureImplemented(FEAT_AA64EL2) &amp;&amp; !ELUsingAArch32(EL2) &amp;&amp; HSTR_EL2().T7 == '1' then
        AArch64_AArch32SystemAccessTrap(EL2, 0x03);
    elsif EL2Enabled() &amp;&amp; IsFeatureImplemented(FEAT_AA32EL2) &amp;&amp; ELUsingAArch32(EL2) &amp;&amp; HSTR().T7 == '1' then
        AArch32_TakeHypTrapException(0x03);
    elsif EL2Enabled() &amp;&amp; IsFeatureImplemented(FEAT_AA32EL2) &amp;&amp; ELUsingAArch32(EL2) &amp;&amp; HCR().FB == '1' then
        BPIALLIS();
    else
        BPIALL();
    end;
elsif PSTATE.EL == EL2 then
    BPIALL();
elsif PSTATE.EL == EL3 then
    BPIALL();
end;
                </pstext>
                </ps>
            </access_permission>
        </access_mechanism>

      </access_mechanisms>

      <arch_variants>
      </arch_variants>
  </register>
</registers>
<timestamp>2026-03-26 20:27:25</timestamp>
<commit_id>2026-03_rel</commit_id>
</register_page>