CCSIDR Current Cache Size ID Register when FEAT_AA32EL1 is implemented CCSIDR_EL1 Architectural AArch64 31 0 31 0 31 0 31 0 Provides information about the architecture of the currently selected cache. When FEAT_CCIDX is implemented, this register is used in conjunction with CCSIDR2. Identification Registers The implementation includes one CCSIDR for each cache that it can access. CSSELR and the Security state select which Cache Size ID Register is accessible. CCSIDR is a 32-bit register. When FEAT_CCIDX is implemented IsFeatureImplemented(FEAT_CCIDX) The parameters NumSets, Associativity, and LineSize in these registers define the architecturally visible parameters that are required for the cache maintenance by Set/Way instructions. They are not guaranteed to represent the actual microarchitectural features of a design. You cannot make any inference about the actual sizes of caches based on these parameters. 31 24 31:24 Reserved, RES0. Associativity 23 3 23:3 (Associativity of cache) - 1, therefore a value of 0 indicates an associativity of 1. The associativity does not have to be a power of 2. LineSize 2 0 2:0 (Log₂(Number of bytes in cache line)) - 4. For example: For a line length of 16 bytes: Log₂(16) = 4, LineSize entry = 0. This is the minimum line length. For a line length of 32 bytes: Log₂(32) = 5, LineSize entry = 1. The C++ 17 specification has two defined parameters relating to the granularity of memory that does not interfere. For generic software and tools, Arm will set the hardware_destructive_interference_size parameter to 256 bytes and the hardware_constructive_interference_size parameter to 64 bytes. !IsFeatureImplemented(FEAT_CCIDX) The parameters NumSets, Associativity, and LineSize in these registers define the architecturally visible parameters that are required for the cache maintenance by Set/Way instructions. They are not guaranteed to represent the actual microarchitectural features of a design. You cannot make any inference about the actual sizes of caches based on these parameters. 31 28 31:28 Reserved, UNKNOWN. NumSets 27 13 27:13 (Number of sets in cache) - 1, therefore a value of 0 indicates 1 set in the cache. The number of sets does not have to be a power of 2. Associativity 12 3 12:3 (Associativity of cache) - 1, therefore a value of 0 indicates an associativity of 1. The associativity does not have to be a power of 2. LineSize 2 0 2:0 (Log₂(Number of bytes in cache line)) - 4. For example: For a line length of 16 bytes: Log₂(16) = 4, LineSize entry = 0. This is the minimum line length. For a line length of 32 bytes: Log₂(32) = 5, LineSize entry = 1. The C++ 17 specification has two defined parameters relating to the granularity of memory that does not interfere. For generic software and tools, Arm will set the hardware_destructive_interference_size parameter to 256 bytes and the hardware_constructive_interference_size parameter to 64 bytes. When FEAT_CCIDX is implemented If CSSELR.{Level, InD} is programmed to a cache level that is not implemented, then on a read of the CCSIDR the behavior is CONSTRAINED UNPREDICTABLE, and can be one of the following: The CCSIDR read is treated as NOP. The CCSIDR read is UNDEFINED. The CCSIDR read returns an UNKNOWN value. MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>} if !IsFeatureImplemented(FEAT_AA32EL1) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T0 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T0 == '1' then AArch32_TakeHypTrapException(0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HCR_EL2().TID2 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && IsFeatureImplemented(FEAT_EVT) && HCR_EL2().TID4 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HCR().TID2 == '1' then AArch32_TakeHypTrapException(0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && IsFeatureImplemented(FEAT_EVT) && HCR2().TID4 == '1' then AArch32_TakeHypTrapException(0x03); else R(t) = CCSIDR(); end; elsif PSTATE.EL == EL2 then R(t) = CCSIDR(); elsif PSTATE.EL == EL3 then R(t) = CCSIDR(); end; 2026-03-26 20:27:25 2026-03_rel