CNTHPS_CTL Counter-timer Secure Physical Timer Control Register (EL2) when FEAT_AA32 is implemented and FEAT_SEL2 is implemented CNTHPS_CTL_EL2 Architectural AArch64 31 0 31 0 31 0 31 0 Provides AArch32 access from EL0 to the Secure EL2 physical timer. Timer This register is banked between CNTHPS_CTL and CNTHPS_CTL_S and CNTHPS_CTL_NS. CNTHPS_CTL is a 32-bit register. This register has the following instances: CNTHPS_CTL, when EL3 is not implemented or FEAT_AA64 is implemented. CNTHPS_CTL_S, when FEAT_AA32EL3 is implemented. CNTHPS_CTL_NS, when FEAT_AA32EL3 is implemented. 31 3 31:3 Reserved, RES0. ISTATUS 2 2 2 The status of the timer. This bit indicates whether the timer condition is met: When the value of the CNTHPS_CTL.ENABLE bit is 1, ISTATUS indicates whether the timer condition is met. ISTATUS takes no account of the value of the IMASK bit. If the value of ISTATUS is 1 and the value of IMASK is 0 then the timer interrupt is asserted. When the value of the CNTHPS_CTL.ENABLE bit is 0, the ISTATUS field is UNKNOWN. 0b0 Timer condition is not met. 0b1 Timer condition is met. AU RO IMASK 1 1 1 Timer interrupt mask bit. Permitted values are: For more information, see the description of the ISTATUS bit. 0b0 Timer interrupt is not masked by the IMASK bit. 0b1 Timer interrupt is masked by the IMASK bit. AU ENABLE 0 0 0 Enables the timer. Permitted values are: Setting this bit to 0 disables the timer output signal, but the timer value accessible from CNTHPS_TVAL continues to count down. Disabling the output signal might be a power-saving option. 0b0 Timer disabled. 0b1 Timer enabled. AU This register is accessed using the encoding for CNTP_CTL. MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>} if !IsFeatureImplemented(FEAT_AA32) then Undefined(); elsif PSTATE.EL == EL0 then if IsFeatureImplemented(FEAT_AA64EL1) && !ELUsingAArch32(EL1) && !ELIsInHost(EL0) && CNTKCTL_EL1().EL0PTEN == '0' then if EL2Enabled() && (IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2)) && HCR_EL2().TGE == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); else AArch64_AArch32SystemAccessTrap(EL1, 0x03); end; elsif IsFeatureImplemented(FEAT_AA32EL1) && ELUsingAArch32(EL1) && CNTKCTL().PL0PTEN == '0' then if EL2Enabled() && (IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2)) && HCR_EL2().TGE == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && (IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2)) && HCR().TGE == '1' then AArch32_TakeHypTrapException(0x00); else Undefined(); end; elsif EL2Enabled() && (IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2)) && !ELIsInHost(EL2) && CNTHCTL_EL2().EL1PCEN == '0' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif ELIsInHost(EL2) && (IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2)) && HCR_EL2().TGE == '0' && CNTHCTL_EL2().EL1PTEN == '0' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif ELIsInHost(EL0) && (IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2)) && CNTHCTL_EL2().EL0PTEN == '0' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && (IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2)) && CNTHCTL().PL1PCEN == '0' then AArch32_TakeHypTrapException(0x03); elsif ELIsInHost(EL0) && IsCurrentSecurityState(SS_Secure) && IsFeatureImplemented(FEAT_SEL2) then R(t) = CNTHPS_CTL_EL2()[31:0]; elsif ELIsInHost(EL0) && !IsCurrentSecurityState(SS_Secure) then R(t) = CNTHP_CTL_EL2()[31:0]; else R(t) = CNTP_CTL(); end; elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && !ELIsInHost(EL2) && CNTHCTL_EL2().EL1PCEN == '0' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif ELIsInHost(EL2) && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && CNTHCTL_EL2().EL1PTEN == '0' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && CNTHCTL().PL1PCEN == '0' then AArch32_TakeHypTrapException(0x03); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) then R(t) = CNTP_CTL_NS(); else R(t) = CNTP_CTL(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) then R(t) = CNTP_CTL_NS(); else R(t) = CNTP_CTL(); end; elsif PSTATE.EL == EL3 then if SCR().NS == '0' then R(t) = CNTP_CTL_S(); else R(t) = CNTP_CTL_NS(); end; end; MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>} if !IsFeatureImplemented(FEAT_AA32) then Undefined(); elsif PSTATE.EL == EL0 then if IsFeatureImplemented(FEAT_AA64EL1) && !ELUsingAArch32(EL1) && !ELIsInHost(EL0) && CNTKCTL_EL1().EL0PTEN == '0' then if EL2Enabled() && (IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2)) && HCR_EL2().TGE == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); else AArch64_AArch32SystemAccessTrap(EL1, 0x03); end; elsif IsFeatureImplemented(FEAT_AA32EL1) && ELUsingAArch32(EL1) && CNTKCTL().PL0PTEN == '0' then if EL2Enabled() && (IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2)) && HCR_EL2().TGE == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && (IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2)) && HCR().TGE == '1' then AArch32_TakeHypTrapException(0x00); else Undefined(); end; elsif EL2Enabled() && (IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2)) && !ELIsInHost(EL2) && CNTHCTL_EL2().EL1PCEN == '0' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif ELIsInHost(EL2) && (IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2)) && HCR_EL2().TGE == '0' && CNTHCTL_EL2().EL1PTEN == '0' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif ELIsInHost(EL0) && (IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2)) && CNTHCTL_EL2().EL0PTEN == '0' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && (IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2)) && CNTHCTL().PL1PCEN == '0' then AArch32_TakeHypTrapException(0x03); elsif ELIsInHost(EL0) && IsCurrentSecurityState(SS_Secure) && IsFeatureImplemented(FEAT_SEL2) then CNTHPS_CTL_EL2()[31:0] = R(t); elsif ELIsInHost(EL0) && !IsCurrentSecurityState(SS_Secure) then CNTHP_CTL_EL2()[31:0] = R(t); else CNTP_CTL() = R(t); end; elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && !ELIsInHost(EL2) && CNTHCTL_EL2().EL1PCEN == '0' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif ELIsInHost(EL2) && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && CNTHCTL_EL2().EL1PTEN == '0' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && CNTHCTL().PL1PCEN == '0' then AArch32_TakeHypTrapException(0x03); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) then CNTP_CTL_NS() = R(t); else CNTP_CTL() = R(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) then CNTP_CTL_NS() = R(t); else CNTP_CTL() = R(t); end; elsif PSTATE.EL == EL3 then if SCR().NS == '0' then CNTP_CTL_S() = R(t); else CNTP_CTL_NS() = R(t); end; end; 2026-03-26 20:27:25 2026-03_rel