CNTKCTL Counter-timer Kernel Control register when FEAT_AA32EL1 is implemented CNTKCTL_EL1 Architectural AArch64 31 0 31 0 31 0 31 0 Controls the generation of an event stream from the virtual counter, and access from EL0 modes to the physical counter, virtual counter, EL1 physical timers, and the virtual timer. Timer CNTKCTL is a 32-bit register. 31 18 31:18 Reserved, RES0. EVNTIS 17 17 0 Controls the scale of the generation of the event stream. This control applies regardless of the value of the CNTHCTL_EL2.ECV bit. 0b0 The CNTKCTL.EVNTI field applies to CNTVCT[15:0]. 0b1 The CNTKCTL.EVNTI field applies to CNTVCT[23:8]. AU When FEAT_ECV is implemented 17 17 17 Reserved, RES0. Otherwise 16 10 16:10 Reserved, RES0. PL0PTEN 9 9 9 Traps PL0 accesses to the physical timer registers to Undefined mode. 0b0 PL0 accesses to the CNTP_CTL, CNTP_CVAL, and CNTP_TVAL registers are trapped to Undefined mode. 0b1 This control does not cause any instructions to be trapped. AU PL0VTEN 8 8 8 Traps PL0 accesses to the virtual timer registers to Undefined mode. 0b0 PL0 accesses to the CNTV_CTL, CNTV_CVAL, and CNTV_TVAL registers are trapped to Undefined mode. 0b1 This control does not cause any instructions to be trapped. AU EVNTI 7 4 7:4 Selects which bit of CNTVCT, as seen from EL1, is the trigger for the event stream generated from that counter when that stream is enabled. If FEAT_ECV is implemented, and CNTKCTL.EVNTIS is 1, this field selects a trigger bit in the range 8 to 23 of CNTVCT. Otherwise, this field selects a trigger bit in the range 0 to 15 of CNTVCT. AU EVNTDIR 3 3 3 Controls which transition of the CNTVCT trigger bit, as seen from EL1 and defined by EVNTI, generates an event when the event stream is enabled. 0b0 A 0 to 1 transition of the trigger bit triggers an event. 0b1 A 1 to 0 transition of the trigger bit triggers an event. AU EVNTEN 2 2 2 Enables the generation of an event stream from CNTVCT as seen from EL1. 0b0 Disables the event stream. 0b1 Enables the event stream. AU PL0VCTEN 1 1 1 Traps PL0 accesses to the frequency register and virtual counter register to Undefined mode. 0b0 PL0 accesses to the CNTVCT are trapped to Undefined mode. PL0 accesses to the CNTFRQ register are trapped to Undefined mode, if CNTKCTL.PL0PCTEN is also 0. 0b1 This control does not cause any instructions to be trapped. AU PL0PCTEN 0 0 0 Traps PL0 accesses to the frequency register and physical counter register to Undefined mode. 0b0 PL0 accesses to the CNTPCT are trapped to Undefined mode. PL0 accesses to the CNTFRQ register are trapped to Undefined mode, if CNTKCTL.PL0VCTEN is also 0. 0b1 This control does not cause any instructions to be trapped. AU MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>} if !IsFeatureImplemented(FEAT_AA32EL1) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then R(t) = CNTKCTL(); elsif PSTATE.EL == EL2 then R(t) = CNTKCTL(); elsif PSTATE.EL == EL3 then R(t) = CNTKCTL(); end; MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>} if !IsFeatureImplemented(FEAT_AA32EL1) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then CNTKCTL() = R(t); elsif PSTATE.EL == EL2 then CNTKCTL() = R(t); elsif PSTATE.EL == EL3 then CNTKCTL() = R(t); end; 2026-03-26 20:27:25 2026-03_rel