CNTP_TVAL Counter-timer Physical Timer TimerValue register when FEAT_AA32 is implemented CNTP_TVAL_EL0 Architectural AArch64 31 0 31 0 31 0 31 0 Holds the timer value for the EL1 physical timer. Timer This register is banked between CNTP_TVAL and CNTP_TVAL_S and CNTP_TVAL_NS. CNTP_TVAL is a 32-bit register. This register has the following instances: CNTP_TVAL, when EL3 is not implemented or FEAT_AA64 is implemented. CNTP_TVAL_S, when FEAT_AA32EL3 is implemented. CNTP_TVAL_NS, when FEAT_AA32EL3 is implemented. TimerValue 31 0 31:0 The TimerValue view of the EL1 physical timer. On a read of this register: If CNTP_CTL.ENABLE is 0, the value returned is UNKNOWN. If CNTP_CTL.ENABLE is 1, the value returned is (CNTP_CVAL - CNTPCT). On a write of this register, CNTP_CVAL is set to (CNTPCT + TimerValue), where TimerValue is treated as a signed 32-bit integer. When CNTP_CTL.ENABLE is 1, the timer condition is met when (CNTPCT - CNTP_CVAL) is greater than or equal to zero. This means that TimerValue acts like a 32-bit downcounter timer. When the timer condition is met: CNTP_CTL.ISTATUS is set to 1. If CNTP_CTL.IMASK is 0, an interrupt is generated. When CNTP_CTL.ENABLE is 0, the TimerValue cannot be read but continues to decrement. When the timer is enabled, the TimerValue represents the elapsed time whether that time was spent enabled or disabled. AU MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>} if !IsFeatureImplemented(FEAT_AA32) then Undefined(); elsif PSTATE.EL == EL0 then if IsFeatureImplemented(FEAT_AA64EL1) && !ELUsingAArch32(EL1) && !ELIsInHost(EL0) && CNTKCTL_EL1().EL0PTEN == '0' then if EL2Enabled() && (IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2)) && HCR_EL2().TGE == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); else AArch64_AArch32SystemAccessTrap(EL1, 0x03); end; elsif IsFeatureImplemented(FEAT_AA32EL1) && ELUsingAArch32(EL1) && CNTKCTL().PL0PTEN == '0' then if EL2Enabled() && (IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2)) && HCR_EL2().TGE == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && (IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2)) && HCR().TGE == '1' then AArch32_TakeHypTrapException(0x00); else Undefined(); end; elsif EL2Enabled() && (IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2)) && !ELIsInHost(EL2) && CNTHCTL_EL2().EL1PCEN == '0' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif ELIsInHost(EL2) && (IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2)) && HCR_EL2().TGE == '0' && CNTHCTL_EL2().EL1PTEN == '0' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif ELIsInHost(EL0) && (IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2)) && CNTHCTL_EL2().EL0PTEN == '0' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && (IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2)) && CNTHCTL().PL1PCEN == '0' then AArch32_TakeHypTrapException(0x03); elsif ELIsInHost(EL0) && IsCurrentSecurityState(SS_Secure) && IsFeatureImplemented(FEAT_SEL2) then if CNTHPS_CTL_EL2().ENABLE == '0' then R(t) = ARBITRARY:bits(32); else R(t) = (CNTHPS_CVAL_EL2() - PhysicalCountInt())[31:0]; end; elsif ELIsInHost(EL0) && !IsCurrentSecurityState(SS_Secure) then if CNTHP_CTL_EL2().ENABLE == '0' then R(t) = ARBITRARY:bits(32); else R(t) = (CNTHP_CVAL_EL2() - PhysicalCountInt())[31:0]; end; elsif IsFeatureImplemented(FEAT_ECV_POFF) && EL2Enabled() && (IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2)) && (!HaveEL(EL3) || SCR_EL3().ECVEn == '1') && CNTHCTL_EL2().ECV == '1' && !ELIsInHost(EL0) then if CNTP_CTL().ENABLE == '0' then R(t) = ARBITRARY:bits(32); else R(t) = (CNTP_CVAL() - (PhysicalCountInt() - CNTPOFF_EL2()))[31:0]; end; elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) then if SCR().NS == '1' then if CNTP_CTL_NS().ENABLE == '0' then R(t) = ARBITRARY:bits(32); else R(t) = (CNTP_CVAL_NS() - PhysicalCountInt())[31:0]; end; else if CNTP_CTL_S().ENABLE == '0' then R(t) = ARBITRARY:bits(32); else R(t) = (CNTP_CVAL_S() - PhysicalCountInt())[31:0]; end; end; else if CNTP_CTL().ENABLE == '0' then R(t) = ARBITRARY:bits(32); else R(t) = (CNTP_CVAL() - PhysicalCountInt())[31:0]; end; end; elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && !ELIsInHost(EL2) && CNTHCTL_EL2().EL1PCEN == '0' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif ELIsInHost(EL2) && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && CNTHCTL_EL2().EL1PTEN == '0' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && CNTHCTL().PL1PCEN == '0' then AArch32_TakeHypTrapException(0x03); elsif IsFeatureImplemented(FEAT_ECV_POFF) && EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && (!HaveEL(EL3) || SCR_EL3().ECVEn == '1') && CNTHCTL_EL2().ECV == '1' then if CNTP_CTL().ENABLE == '0' then R(t) = ARBITRARY:bits(32); else R(t) = (CNTP_CVAL() - (PhysicalCountInt() - CNTPOFF_EL2()))[31:0]; end; elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) then if CNTP_CTL_NS().ENABLE == '0' then R(t) = ARBITRARY:bits(32); else R(t) = (CNTP_CVAL_NS() - PhysicalCountInt())[31:0]; end; else if CNTP_CTL().ENABLE == '0' then R(t) = ARBITRARY:bits(32); else R(t) = (CNTP_CVAL() - PhysicalCountInt())[31:0]; end; end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) then if CNTP_CTL_NS().ENABLE == '0' then R(t) = ARBITRARY:bits(32); else R(t) = (CNTP_CVAL_NS() - PhysicalCountInt())[31:0]; end; else if CNTP_CTL().ENABLE == '0' then R(t) = ARBITRARY:bits(32); else R(t) = (CNTP_CVAL() - PhysicalCountInt())[31:0]; end; end; elsif PSTATE.EL == EL3 then if SCR().NS == '0' then if CNTP_CTL_S().ENABLE == '0' then R(t) = ARBITRARY:bits(32); else R(t) = (CNTP_CVAL_S() - PhysicalCountInt())[31:0]; end; else if CNTP_CTL_NS().ENABLE == '0' then R(t) = ARBITRARY:bits(32); else R(t) = (CNTP_CVAL_NS() - PhysicalCountInt())[31:0]; end; end; end; MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>} if !IsFeatureImplemented(FEAT_AA32) then Undefined(); elsif PSTATE.EL == EL0 then if IsFeatureImplemented(FEAT_AA64EL1) && !ELUsingAArch32(EL1) && !ELIsInHost(EL0) && CNTKCTL_EL1().EL0PTEN == '0' then if EL2Enabled() && (IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2)) && HCR_EL2().TGE == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); else AArch64_AArch32SystemAccessTrap(EL1, 0x03); end; elsif IsFeatureImplemented(FEAT_AA32EL1) && ELUsingAArch32(EL1) && CNTKCTL().PL0PTEN == '0' then if EL2Enabled() && (IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2)) && HCR_EL2().TGE == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && (IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2)) && HCR().TGE == '1' then AArch32_TakeHypTrapException(0x00); else Undefined(); end; elsif EL2Enabled() && (IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2)) && !ELIsInHost(EL2) && CNTHCTL_EL2().EL1PCEN == '0' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif ELIsInHost(EL2) && (IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2)) && HCR_EL2().TGE == '0' && CNTHCTL_EL2().EL1PTEN == '0' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif ELIsInHost(EL0) && (IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2)) && CNTHCTL_EL2().EL0PTEN == '0' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && (IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2)) && CNTHCTL().PL1PCEN == '0' then AArch32_TakeHypTrapException(0x03); elsif ELIsInHost(EL0) && IsCurrentSecurityState(SS_Secure) && IsFeatureImplemented(FEAT_SEL2) then CNTHPS_CVAL_EL2() = SignExtend{64}(R(t)) + PhysicalCountInt(); elsif ELIsInHost(EL0) && !IsCurrentSecurityState(SS_Secure) then CNTHP_CVAL_EL2() = SignExtend{64}(R(t)) + PhysicalCountInt(); elsif IsFeatureImplemented(FEAT_ECV_POFF) && EL2Enabled() && (IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2)) && (!HaveEL(EL3) || SCR_EL3().ECVEn == '1') && CNTHCTL_EL2().ECV == '1' && !ELIsInHost(EL0) then CNTP_CVAL() = (SignExtend{64}(R(t)) + PhysicalCountInt()) - CNTPOFF_EL2(); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) then if SCR().NS == '1' then CNTP_CVAL_NS() = SignExtend{64}(R(t)) + PhysicalCountInt(); else CNTP_CVAL_S() = SignExtend{64}(R(t)) + PhysicalCountInt(); end; else CNTP_CVAL() = SignExtend{64}(R(t)) + PhysicalCountInt(); end; elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && !ELIsInHost(EL2) && CNTHCTL_EL2().EL1PCEN == '0' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif ELIsInHost(EL2) && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && CNTHCTL_EL2().EL1PTEN == '0' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && CNTHCTL().PL1PCEN == '0' then AArch32_TakeHypTrapException(0x03); elsif IsFeatureImplemented(FEAT_ECV_POFF) && EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && (!HaveEL(EL3) || SCR_EL3().ECVEn == '1') && CNTHCTL_EL2().ECV == '1' then CNTP_CVAL() = (SignExtend{64}(R(t)) + PhysicalCountInt()) - CNTPOFF_EL2(); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) then CNTP_CVAL_NS() = SignExtend{64}(R(t)) + PhysicalCountInt(); else CNTP_CVAL() = SignExtend{64}(R(t)) + PhysicalCountInt(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) then CNTP_CVAL_NS() = SignExtend{64}(R(t)) + PhysicalCountInt(); else CNTP_CVAL() = SignExtend{64}(R(t)) + PhysicalCountInt(); end; elsif PSTATE.EL == EL3 then if SCR().NS == '0' then CNTP_CVAL_S() = SignExtend{64}(R(t)) + PhysicalCountInt(); else CNTP_CVAL_NS() = SignExtend{64}(R(t)) + PhysicalCountInt(); end; end; 2026-03-26 20:27:25 2026-03_rel