CNTVOFF Counter-timer Virtual Offset register when FEAT_AA32EL2 is implemented When EL2 is implemented and can use AArch32, on a reset into an Exception level that is using AArch32 this register resets to an IMPLEMENTATION DEFINED value that might be UNKNOWN. CNTVOFF_EL2 Architectural AArch64 63 0 63 0 63 0 63 0 Holds the 64-bit virtual offset. This is the offset between the physical count value visible in CNTPCT and the virtual count value visible in CNTVCT. Virt If EL2 is not implemented, this register is RES0 from EL3 and the virtual counter uses a fixed virtual offset of zero. When the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}, the virtual counter uses a fixed virtual offset of zero when CNTVCT is read from Non-secure EL0. CNTVOFF is a 64-bit register. VOffset Virtual offset 63 0 63:0 Virtual offset. If the Generic counter is implemented at a size less than 64 bits, then this field is permitted to be implemented at the same width as the counter, and the upper bits are RES0. The value of this field is treated as zero-extended in all counter calculations. AU MRRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <Rt2>, <CRm> if !IsFeatureImplemented(FEAT_AA32EL2) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then Undefined(); elsif PSTATE.EL == EL2 then R(t, t2) = CNTVOFF(); elsif PSTATE.EL == EL3 then if SCR().NS == '0' then Undefined(); else R(t, t2) = CNTVOFF(); end; end; MCRR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <Rt2>, <CRm> if !IsFeatureImplemented(FEAT_AA32EL2) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then Undefined(); elsif PSTATE.EL == EL2 then CNTVOFF() = R(t, t2); elsif PSTATE.EL == EL3 then if SCR().NS == '0' then Undefined(); else CNTVOFF() = R(t, t2); end; end; 2026-03-26 20:27:25 2026-03_rel