CPACR
Architectural Feature Access Control Register
when FEAT_AA32EL1 is implemented
CPACR_EL1
Architectural
AArch64
31
0
31
0
31
0
31
0
Controls access to trace, and to Advanced SIMD and floating-point functionality from EL0, EL1, and EL3.
In an implementation that includes EL2, the CPACR has no effect on instructions executed at EL2.
Other
Bits in the NSACR control Non-secure access to the CPACR fields. See the field descriptions for more information.
In the register field descriptions, controls are described as applying at specified Privilege levels. This is because, in Secure state, a PL1 control:Applies to execution in a Secure EL3 mode when EL3 is using AArch32.Applies to execution in a Secure EL1 mode when EL3 is using AArch64.
See 'Security state, Exception levels, and AArch32 execution privilege'.
CPACR is a 32-bit register.
ASEDIS
31
31
31
Disables PL0 and PL1 execution of Advanced SIMD instructions.
If the implementation does not include Advanced SIMD and floating-point functionality, this field is RES0. Otherwise, it is IMPLEMENTATION DEFINED whether this field is implemented as a RW field. If it is not implemented as a RW field, it is RAZ/WI.
If EL3 is implemented and is using AArch32, and the value of NSACR.NSASEDIS is 1, this field behaves as RAO/WI in Non-secure state, regardless of its actual value. This applies even if the field is implemented as RAZ/WI.
For the list of instructions affected by this field, see 'Controls of Advanced SIMD operation that do not apply to floating-point operation'.
See the description of CPACR.cp10 for a list of other controls that can disable or trap execution of Advanced SIMD instructions in AArch32 state.
0b0
This control permits execution of Advanced SIMD instructions at PL0 and PL1.
0b1
All instruction encodings that are Advanced SIMD instruction encodings, but are not also floating-point instruction encodings, are UNDEFINED at PL0 and PL1.
'0'
30
29
30:29
Reserved, RES0.
TRCDIS
28
28
28
Traps PL0 and PL1 System register accesses to all implemented trace System registers to Undefined mode.
If the implementation does not include a trace unit, or does not include a System register interface to the trace unit registers, this field is RES0. Otherwise, it is IMPLEMENTATION DEFINED whether this field is implemented as a RW field. If it is not implemented as a RW field, it is RAZ/WI.
If EL3 is implemented and is using AArch32, and the value of NSACR.NSTRCDIS is 1, this field behaves as RAO/WI in Non-secure state, regardless of its actual value. This applies even if the field is implemented as RAZ/WI.
FEAT_ETMv4 and FEAT_ETE do not permit EL0 to access the trace System registers. EL0 accesses to the trace System registers are UNDEFINED.The Arm architecture does not provide traps on trace register accesses through the optional memory-mapped external debug interface.
System register accesses to the trace System registers can have side-effects. When a System register access is trapped, any side-effects that are normally associated with the access do not occur before the exception is taken.
0b0
This control has no effect on PL0 and PL1 System register accesses to trace System registers.
0b1
PL0 and PL1 System register accesses to all implemented trace System registers are trapped to Undefined mode.
AU
27
24
27:24
Reserved, RES0.
cp11
23
22
23:22
The value of this field is ignored. If this field is programmed with a different value to the cp10 field then this field is UNKNOWN on a direct read of the CPACR.
If the implementation does not include Advanced SIMD and floating-point functionality, this field is RES0.
In Non-secure state, if EL3 is implemented and is using AArch32, when the value of NSACR.cp10 is 0, this field behaves as RAZ/WI, regardless of its actual value.
'00'
EL3 is implemented
EL3 is using AArch32
!IsCurrentSecurityState(SS_Secure)
NSACR.cp10 == '0'
RAZ/WI
cp10
21
20
21:20
Defines the access rights for the Advanced SIMD and floating-point functionality. Possible values of the field are:
The Advanced SIMD and floating-point features controlled by these fields are:
Execution of any floating-point or Advanced SIMD instruction.
Any access to the Advanced SIMD and floating-point registers D0-D31 and their views as S0-S31 and Q0-Q15.
Any access to the FPSCR, FPSID, MVFR0, MVFR1, MVFR2, or FPEXC System registers.
The CPACR has no effect on Advanced SIMD and floating-point accesses from PL2. These can be disabled by the HCPTR.TCP10 field.If the implementation does not include Advanced SIMD and floating-point functionality, this field is RES0.
In Non-secure state, if EL3 is implemented and is using AArch32, when the value of NSACR.cp10 is 0, this field behaves as RAZ/WI, regardless of its actual value.
Execution of Advanced SIMD and floating-point instructions in AArch32 state can be disabled or trapped by the following controls:
CPACR.cp10, or, if executing at EL0, CPACR_EL1.FPEN.
FPEXC.EN.
If executing in Non-secure state:
HCPTR.TCP10, or if EL2 is using AArch64, CPTR_EL2.TFP.
NSACR.cp10, or if EL3 is using AArch64, CPTR_EL3.TFP.
For Advanced SIMD instructions only:
CPACR.ASEDIS.
If executing in Non-secure state, HCPTR.TASE and NSACR.NSASEDIS.
See the descriptions of the controls for more information.
0b00
PL0 and PL1 accesses to Advanced SIMD and floating-point registers or instructions are UNDEFINED.
0b01
PL0 accesses to Advanced SIMD and floating-point registers or instructions are UNDEFINED.
0b10
Reserved. The effect of programming this field to this value is CONSTRAINED UNPREDICTABLE choice between:
The value of this field is treated as 0b00, 0b01, or 0b11 for all purposes other than reading the value of the field.
PL1 accesses to floating-point and Advanced SIMD registers or instructions are UNDEFINED.
0b11
This control permits full access to the Advanced SIMD and floating-point functionality from PL0 and PL1.
'00'
EL3 is implemented
EL3 is using AArch32
!IsCurrentSecurityState(SS_Secure)
NSACR.cp10 == '0'
RAZ/WI
19
0
19:0
Reserved, RES0.
MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
if !IsFeatureImplemented(FEAT_AA32EL1) then
Undefined();
elsif PSTATE.EL == EL0 then
Undefined();
elsif PSTATE.EL == EL1 then
if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && CPTR_EL3().TCPAC == '1' then
Undefined();
elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T1 == '1' then
AArch64_AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T1 == '1' then
AArch32_TakeHypTrapException(0x03);
elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && CPTR_EL2().TCPAC == '1' then
AArch64_AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HCPTR().TCPAC == '1' then
AArch32_TakeHypTrapException(0x03);
elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && CPTR_EL3().TCPAC == '1' then
if EL3SDDUndef() then
Undefined();
else
AArch64_AArch32SystemAccessTrap(EL3, 0x03);
end;
else
R(t) = CPACR();
end;
elsif PSTATE.EL == EL2 then
if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && CPTR_EL3().TCPAC == '1' then
Undefined();
elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && CPTR_EL3().TCPAC == '1' then
if EL3SDDUndef() then
Undefined();
else
AArch64_AArch32SystemAccessTrap(EL3, 0x03);
end;
else
R(t) = CPACR();
end;
elsif PSTATE.EL == EL3 then
R(t) = CPACR();
end;
MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
if !IsFeatureImplemented(FEAT_AA32EL1) then
Undefined();
elsif PSTATE.EL == EL0 then
Undefined();
elsif PSTATE.EL == EL1 then
if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && CPTR_EL3().TCPAC == '1' then
Undefined();
elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T1 == '1' then
AArch64_AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T1 == '1' then
AArch32_TakeHypTrapException(0x03);
elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && CPTR_EL2().TCPAC == '1' then
AArch64_AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HCPTR().TCPAC == '1' then
AArch32_TakeHypTrapException(0x03);
elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && CPTR_EL3().TCPAC == '1' then
if EL3SDDUndef() then
Undefined();
else
AArch64_AArch32SystemAccessTrap(EL3, 0x03);
end;
else
CPACR() = R(t);
end;
elsif PSTATE.EL == EL2 then
if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && CPTR_EL3().TCPAC == '1' then
Undefined();
elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && CPTR_EL3().TCPAC == '1' then
if EL3SDDUndef() then
Undefined();
else
AArch64_AArch32SystemAccessTrap(EL3, 0x03);
end;
else
CPACR() = R(t);
end;
elsif PSTATE.EL == EL3 then
CPACR() = R(t);
end;
2026-03-26 20:27:25
2026-03_rel