CPSR Current Program Status Register when FEAT_AA32 is implemented Holds PE status and control information. PSTATE CPSR is a 32-bit register. N 31 31 31 Negative condition flag. Set to bit[31] of the result of the last flag-setting instruction. If the result is regarded as a two's complement signed integer, then N is set to 1 if the result was negative, and N is set to 0 if the result was positive or zero. Z 30 30 30 Zero condition flag. Set to 1 if the result of the last flag-setting instruction was zero, and to 0 otherwise. A result of zero often indicates an equal result from a comparison. C 29 29 29 Carry condition flag. Set to 1 if the last flag-setting instruction resulted in a carry condition, for example an unsigned overflow on an addition. V 28 28 28 Overflow condition flag. Set to 1 if the last flag-setting instruction resulted in an overflow condition, for example a signed overflow on an addition. Q 27 27 27 Cumulative saturation bit. Set to 1 to indicate that overflow or saturation occurred in some instructions. 26 24 26:24 Reserved, RES0. SSBS 23 23 0 Speculative Store Bypass Safe. Prohibits speculative loads or stores that might practically allow a cache timing side channel. A speculative value in a register is used in a potentially speculatively exploitable manner if it is used to form an address, generate condition codes, or generate SVE predicate values to be used by other instructions in the speculative sequence or if the execution timing of any other instructions in the speculative sequence is a function of the data loaded under speculation. The value of this bit is usually set to the value described by the SCTLR.DSSBS bit on exceptions to any mode except Hyp mode, and the value described by HSCTLR.DSSBS on exceptions to Hyp mode. 0b0 Hardware is not permitted to use speculative register values in a potentially speculatively exploitable manner if the speculative read that loads the register is from earlier in the coherence order than the entry generated by the latest store to that location using the same virtual address as the load instruction. 0b1 When the value of PSTATE.SSBS is 1, hardware is permitted to use speculative register values in a potentially speculatively exploitable manner if the speculative read that loads the register is from earlier in the coherence order than the entry generated by the latest store to that location using the same virtual address as the load instruction. ID When FEAT_SSBS is implemented 23 23 23 Reserved, RES0. Otherwise PAN 22 22 0 Privileged Access Never. The value of this bit is usually preserved on taking an exception, except in the following situations: When the target of the exception is EL1, and the value of the SCTLR.SPAN bit for the current Security state is 0, this bit is set to 1. When the target of the exception is EL3, from Secure state, and the value of the Secure SCTLR.SPAN is 0, this bit is set to 1. When the target of the exception is EL3, from Non-secure state, this bit is set to 0 regardless of the value of the Secure SCTLR.SPAN bit. 0b0 The translation system is the same as Armv8.0. 0b1 Disables privileged read and write accesses to addresses accessible at EL0. When FEAT_PAN is implemented 22 22 22 Reserved, RES0. Otherwise DIT 21 21 0 Data Independent Timing. The Operational Information section of a data processing instruction description indicates if that instruction is affected by this bit. 0b0 The architecture makes no statement about the timing properties of any instructions. 0b1 The architecture requires that the execution time of a data-independent-time sequence of code must be independent of all data-independent-time values. For more information, see About the DIT bit. '0' When FEAT_DIT is implemented 21 21 21 Reserved, RES0. Otherwise 20 20 20 Reserved, RES0. GE 19 16 19:16 Greater than or Equal flags, for parallel addition and subtraction. 15 10 15:10 Reserved, RES0. E 9 9 9 Endianness state bit. Controls the load and store endianness for data accesses: Instruction fetches ignore this bit. If an implementation does not provide Big-endian support, this bit is RES0. If it does not provide Little-endian support, this bit is RES1. If an implementation provides Big-endian support but only at EL0, this bit is RES0 for an exception return to any Exception level other than EL0. Likewise, if it provides Little-endian support only at EL0, this bit is RES1 for an exception return to any Exception level other than EL0. 0b0 Little-endian operation 0b1 Big-endian operation. When the reset value of the SCTLR.EE bit is defined by a configuration input signal, that value also applies to the CPSR.E bit on reset, and therefore applies to software execution from reset. A 8 8 8 SError exception mask bit. 0b0 Exception not masked. 0b1 Exception masked. I 7 7 7 IRQ mask bit. 0b0 Exception not masked. 0b1 Exception masked. F 6 6 6 FIQ mask bit. 0b0 Exception not masked. 0b1 Exception masked. 5 5 5 Reserved, RES0. 4 4 4 Reserved, RES1. M 3 0 3:0 Current PE mode. 0b0000 User. 0b0001 FIQ. 0b0010 IRQ. 0b0011 Supervisor. 0b0110 Monitor. 0b0111 Abort. 0b1010 Hyp. 0b1011 Undefined. 0b1111 System. CPSR can be read using the MRS instruction and written using the MSR (register) or MSR (immediate) instructions. The MSR (register) and MRS instructions used to access CPSR are data-independent-time instructions as described in About PSTATE.DIT. 2026-03-26 20:27:25 2026-03_rel