CSSELR Cache Size Selection Register when FEAT_AA32EL1 is implemented CSSELR_EL1 Architectural AArch64 31 0 31 0 31 0 31 0 Selects the current Cache Size ID Register, CCSIDR, by specifying the required cache level and the cache type, which is either instruction cache or data cache. If FEAT_CCIDX is implemented, CSSELR also selects the current CCSIDR2. Identification Registers This register is banked between CSSELR and CSSELR_S and CSSELR_NS. CSSELR is a 32-bit register. This register has the following instances: CSSELR, when EL3 is not implemented or FEAT_AA64 is implemented. CSSELR_S, when FEAT_AA32EL3 is implemented. CSSELR_NS, when FEAT_AA32EL3 is implemented. 31 4 31:4 Reserved, RES0. Level 3 1 3:1 Cache level of required cache. Permitted values are: All other values are reserved. If CSSELR.{Level, InD} is programmed to a cache level that is not implemented, then the value for this field on a read of CSSELR is UNKNOWN. 0b000 Level 1 cache. 0b001 Level 2 cache. 0b010 Level 3 cache. 0b011 Level 4 cache. 0b100 Level 5 cache. 0b101 Level 6 cache. 0b110 Level 7 cache. AU InD 0 0 0 Instruction not Data bit. Permitted values are: If CSSELR.{Level, InD} is programmed to a cache level that is not implemented, then the value for this field on a read of CSSELR is UNKNOWN. 0b0 Data or unified cache. 0b1 Instruction cache. AU MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>} if !IsFeatureImplemented(FEAT_AA32EL1) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T0 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T0 == '1' then AArch32_TakeHypTrapException(0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HCR_EL2().TID2 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && IsFeatureImplemented(FEAT_EVT) && HCR_EL2().TID4 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HCR().TID2 == '1' then AArch32_TakeHypTrapException(0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && IsFeatureImplemented(FEAT_EVT) && HCR2().TID4 == '1' then AArch32_TakeHypTrapException(0x03); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) then R(t) = CSSELR_NS(); else R(t) = CSSELR(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) then R(t) = CSSELR_NS(); else R(t) = CSSELR(); end; elsif PSTATE.EL == EL3 then if SCR().NS == '0' then R(t) = CSSELR_S(); else R(t) = CSSELR_NS(); end; end; MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>} if !IsFeatureImplemented(FEAT_AA32EL1) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T0 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T0 == '1' then AArch32_TakeHypTrapException(0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HCR_EL2().TID2 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && IsFeatureImplemented(FEAT_EVT) && HCR_EL2().TID4 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HCR().TID2 == '1' then AArch32_TakeHypTrapException(0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && IsFeatureImplemented(FEAT_EVT) && HCR2().TID4 == '1' then AArch32_TakeHypTrapException(0x03); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) then CSSELR_NS() = R(t); else CSSELR() = R(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) then CSSELR_NS() = R(t); else CSSELR() = R(t); end; elsif PSTATE.EL == EL3 then if SCR().NS == '0' then CSSELR_S() = R(t); else CSSELR_NS() = R(t); end; end; 2026-03-26 20:27:25 2026-03_rel