DBGBCR<n>
Debug Breakpoint Control Registers
when FEAT_AA32EL1 is implemented
0
15
DBGBCR<n>_EL1
Architectural
AArch64
31
0
31
0
31
0
31
0
DBGBCR<n>_EL1
Architectural
External
31
0
31
0
31
0
31
0
Holds control information for a breakpoint.
Forms breakpoint n together with value register DBGBVR<n>.
If EL2 is implemented and this breakpoint supports Context matching,
DBGBVR<n> can be associated with a Breakpoint Extended Value
Register DBGBXVR<n> for VMID matching.
Debug
If breakpoint n is not implemented then accesses to this register are UNDEFINED.
DBGBCR<n> is a 32-bit register.
When the E field is zero, all the other fields in the register are ignored.
31
24
31:24
Reserved, RES0.
BT
23
20
23:20
Breakpoint Type. Possible values are:
For more information on Breakpoints and their constraints, see 'Breakpoint exceptions' and 'Reserved DBGBCR<n>.BT values'.
0b0000
Unlinked instruction address match. DBGBVR<n> is the address of an instruction.
0b0001
As 0b0000, but linked to a Context matching breakpoint.
0b0010
Unlinked Context ID match. If the Effective value of HCR_EL2.E2H is 1, and either the PE is executing at EL0 with HCR_EL2.TGE set to 1 or the PE is executing at EL2, then DBGBVR<n>.ContextID is compared against CONTEXTIDR_EL2. Otherwise, DBGBVR<n>.ContextID is compared against CONTEXTIDR.
0b0011
As 0b0010 with linking enabled.
0b0100
Unlinked instruction address mismatch. DBGBVR<n> is the address of an instruction to be stepped.
0b0101
As 0b0100, but linked to a Context matching breakpoint.
0b0110
Unlinked CONTEXTIDR match. DBGBVR<n>.ContextID is a Context ID compared against CONTEXTIDR.
0b0111
As 0b0110 with linking enabled.
0b1000
Unlinked VMID match. DBGBXVR<n>.VMID is a VMID compared against VTTBR.VMID.
0b1001
As 0b1000 with linking enabled.
0b1010
Unlinked VMID and Context ID match. DBGBVR<n>.ContextID is a Context ID compared against CONTEXTIDR, and DBGBXVR<n>.VMID is a VMID compared against VTTBR.VMID.
0b1011
As 0b1010 with linking enabled.
0b1100
Unlinked CONTEXTIDR_EL2 match. DBGBXVR<n>.ContextID2 is a Context ID compared against CONTEXTIDR_EL2.
0b1101
As 0b1100 with linking enabled.
0b1110
Unlinked Full Context ID match. DBGBVR<n>.ContextID is compared against CONTEXTIDR, and DBGBXVR<n>.ContextID2 is compared against CONTEXTIDR_EL2.
0b1111
As 0b1110 with linking enabled.
AU
LBN
19
16
19:16
Linked Breakpoint Number. For Linked address matching breakpoints, this specifies the index of the context-matching breakpoint linked to.
For all other breakpoint types, this field is ignored and reads of the register return an UNKNOWN value.
This field is ignored when the value of DBGBCR<n>.E is 0.
AU
SSC
15
14
15:14
Security state control. Determines the Security states under which a Breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the HMC and PMC fields, and there are constraints on the permitted values of the {HMC, SSC, PMC} fields.
For more information, see 'Execution conditions for which a breakpoint generates Breakpoint exceptions' and 'Reserved DBGBCR<n>.{SSC, HMC, PMC} values'.
AU
HMC
13
13
13
Higher mode control. Determines the debug perspective for deciding when a Breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the SSC and PMC fields, and there are constraints on the permitted values of the {HMC, SSC, PMC} fields. For more information see the SSC, bits [15:14] description.
For more information on the operation of the SSC, HMC, and PMC fields, see 'Execution conditions for which a breakpoint generates Breakpoint exceptions'.
AU
12
9
12:9
Reserved, RES0.
BAS
8
5
8:5
Byte address select. Defines which halfwords an address-matching breakpoint matches, regardless of the instruction set and Execution state.
The permitted values depend on the breakpoint type.
For Address match breakpoints, the permitted values are:
BASMatch instruction atConstraint for debuggers
0b0011DBGBVR<n>Use for T32 instructions
0b1100DBGBVR<n>+2Use for T32 instructions
0b1111DBGBVR<n>Use for A32 instructions
All other values are reserved. For more information, see 'Reserved DBGBCR<n>.BAS values'.
For more information on using the BAS field in Address Match breakpoints, see 'Using the BAS field in Address Match breakpoints'.
For Address mismatch breakpoints in an AArch32 stage 1 translation regime, the permitted values are:
BASStep instruction atConstraint for debuggers
0b0000-Use for a match anywhere breakpoint
0b0011DBGBVR<n>Use for T32 instructions
0b1100DBGBVR<n>+2Use for T32 instructions
0b1111DBGBVR<n>Use for A32 instructions
All other values are reserved. For more information, see 'Reserved DBGBCR<n>.BAS values'.
For more information on using the BAS field in address mismatch breakpoints, see 'Using the BAS field in Address Match breakpoints'.
For Context matching breakpoints, this field is RES1 and ignored.
AU
4
3
4:3
Reserved, RES0.
PMC
2
1
2:1
Privilege mode control. Determines the Exception level or levels at which a Breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the SSC and HMC fields, and there are constraints on the permitted values of the {HMC, SSC, PMC} fields. For more information see the DBGBCR<n>.SSC description.
For more information on the operation of the SSC, HMC, and PMC fields, see 'Execution conditions for which a breakpoint generates Breakpoint exceptions'.
AU
E
0
0
0
Enable breakpoint DBGBVR<n>. Possible values are:
0b0
Breakpoint disabled.
0b1
Breakpoint enabled.
AU
0-15
MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
let m:integer = UInt(CRm[3:0]);
if !IsFeatureImplemented(FEAT_AA32EL1) then
Undefined();
elsif m >= NUM_BREAKPOINTS then
Undefined();
elsif PSTATE.EL == EL0 then
Undefined();
elsif PSTATE.EL == EL1 then
if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3().TDA == '1' then
Undefined();
elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && MDCR_EL2().[TDE,TDA] != '00' then
AArch64_AArch32SystemAccessTrap(EL2, 0x05);
elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HDCR().[TDE,TDA] != '00' then
AArch32_TakeHypTrapException(0x05);
elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3().TDA == '1' then
if EL3SDDUndef() then
Undefined();
else
AArch64_AArch32SystemAccessTrap(EL3, 0x05);
end;
elsif DBGOSLSR().OSLK == '0' && HaltingAllowed() && EDSCR().TDA == '1' then
Halt(DebugHalt_SoftwareAccess);
else
R(t) = DBGBCR(m);
end;
elsif PSTATE.EL == EL2 then
if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3().TDA == '1' then
Undefined();
elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3().TDA == '1' then
if EL3SDDUndef() then
Undefined();
else
AArch64_AArch32SystemAccessTrap(EL3, 0x05);
end;
elsif DBGOSLSR().OSLK == '0' && HaltingAllowed() && EDSCR().TDA == '1' then
Halt(DebugHalt_SoftwareAccess);
else
R(t) = DBGBCR(m);
end;
elsif PSTATE.EL == EL3 then
if DBGOSLSR().OSLK == '0' && HaltingAllowed() && EDSCR().TDA == '1' then
Halt(DebugHalt_SoftwareAccess);
else
R(t) = DBGBCR(m);
end;
end;
0-15
MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
let m:integer = UInt(CRm[3:0]);
if !IsFeatureImplemented(FEAT_AA32EL1) then
Undefined();
elsif m >= NUM_BREAKPOINTS then
Undefined();
elsif PSTATE.EL == EL0 then
Undefined();
elsif PSTATE.EL == EL1 then
if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3().TDA == '1' then
Undefined();
elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && MDCR_EL2().[TDE,TDA] != '00' then
AArch64_AArch32SystemAccessTrap(EL2, 0x05);
elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HDCR().[TDE,TDA] != '00' then
AArch32_TakeHypTrapException(0x05);
elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3().TDA == '1' then
if EL3SDDUndef() then
Undefined();
else
AArch64_AArch32SystemAccessTrap(EL3, 0x05);
end;
elsif DBGOSLSR().OSLK == '0' && HaltingAllowed() && EDSCR().TDA == '1' then
Halt(DebugHalt_SoftwareAccess);
else
DBGBCR(m) = R(t);
end;
elsif PSTATE.EL == EL2 then
if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3().TDA == '1' then
Undefined();
elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3().TDA == '1' then
if EL3SDDUndef() then
Undefined();
else
AArch64_AArch32SystemAccessTrap(EL3, 0x05);
end;
elsif DBGOSLSR().OSLK == '0' && HaltingAllowed() && EDSCR().TDA == '1' then
Halt(DebugHalt_SoftwareAccess);
else
DBGBCR(m) = R(t);
end;
elsif PSTATE.EL == EL3 then
if DBGOSLSR().OSLK == '0' && HaltingAllowed() && EDSCR().TDA == '1' then
Halt(DebugHalt_SoftwareAccess);
else
DBGBCR(m) = R(t);
end;
end;
2026-03-26 20:27:25
2026-03_rel