DBGBVR<n> Debug Breakpoint Value Registers when FEAT_AA32EL1 is implemented 0 15 DBGBVR<n>_EL1 Architectural AArch64 31 0 31 0 31 0 31 0 DBGBVR<n>_EL1 Architectural External 31 0 31 0 31 0 31 0 Holds a value for use in breakpoint matching, either the virtual address of an instruction or a context ID. Forms breakpoint n together with control register DBGBCR<n>. If EL2 is implemented and this breakpoint supports Context matching, DBGBVR<n> can be associated with a Breakpoint Extended Value Register DBGBXVR<n> for VMID matching. Debug How this register is interpreted depends on the value of DBGBCR<n>.BT. When DBGBCR<n>.BT is 0b0x0x, this register holds a virtual address. When DBGBCR<n>.BT is 0bxx1x, this register holds a Context ID. For other values of DBGBCR<n>.BT, this register is RES0. Some breakpoints might not support Context ID comparison. For more information, see the description of the DBGDIDR.CTX_CMPs field. If breakpoint n is not implemented then accesses to this register are UNDEFINED. DBGBVR<n> is a 32-bit register. When DBGBCR<n>.BT IN {'0x0x'} DBGBCR<n>.BT==0b0x0x VA[31:2] 31 2 31:2 Bits[31:2] of the address value for comparison. AU 1 0 1:0 Reserved, RES0. When DBGBCR<n>.BT IN {'001x'} DBGBCR<n>.BT==0b001x ContextID 31 0 31:0 Context ID value for comparison. The value is compared against CONTEXTIDR_EL2 when all of the following are true: The Effective value of HCR_EL2.{E2H, TGE} is {1, 1}. The PE is executing at EL0. Otherwise, the value is compared against CONTEXTIDR. AU When DBGBCR<n>.BT IN {'101x'} and EL2 is implemented DBGBCR<n>.BT==0b101x and EL2 is implemented ContextID 31 0 31:0 Context ID value for comparison against CONTEXTIDR. AU When DBGBCR<n>.BT IN {'x11x'}, EL2 is implemented, and FEAT_Debugv8p1 is implemented DBGBCR<n>.BT==0bx11x, EL2 is implemented, and FEAT_Debugv8p1 is implemented ContextID 31 0 31:0 Context ID value for comparison against CONTEXTIDR. AU When DBGBCR<n>.BT IN {'0x0x'} When DBGBCR<n>.BT IN {'001x'} When DBGBCR<n>.BT IN {'101x'} and EL2 is implemented When DBGBCR<n>.BT IN {'x11x'}, EL2 is implemented, and FEAT_Debugv8p1 is implemented 0-15 MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>} let m:integer = UInt(CRm[3:0]); if !IsFeatureImplemented(FEAT_AA32EL1) then Undefined(); elsif m >= NUM_BREAKPOINTS then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3().TDA == '1' then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && MDCR_EL2().[TDE,TDA] != '00' then AArch64_AArch32SystemAccessTrap(EL2, 0x05); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HDCR().[TDE,TDA] != '00' then AArch32_TakeHypTrapException(0x05); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3().TDA == '1' then if EL3SDDUndef() then Undefined(); else AArch64_AArch32SystemAccessTrap(EL3, 0x05); end; elsif DBGOSLSR().OSLK == '0' && HaltingAllowed() && EDSCR().TDA == '1' then Halt(DebugHalt_SoftwareAccess); else R(t) = DBGBVR(m); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3().TDA == '1' then Undefined(); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3().TDA == '1' then if EL3SDDUndef() then Undefined(); else AArch64_AArch32SystemAccessTrap(EL3, 0x05); end; elsif DBGOSLSR().OSLK == '0' && HaltingAllowed() && EDSCR().TDA == '1' then Halt(DebugHalt_SoftwareAccess); else R(t) = DBGBVR(m); end; elsif PSTATE.EL == EL3 then if DBGOSLSR().OSLK == '0' && HaltingAllowed() && EDSCR().TDA == '1' then Halt(DebugHalt_SoftwareAccess); else R(t) = DBGBVR(m); end; end; 0-15 MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>} let m:integer = UInt(CRm[3:0]); if !IsFeatureImplemented(FEAT_AA32EL1) then Undefined(); elsif m >= NUM_BREAKPOINTS then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3().TDA == '1' then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && MDCR_EL2().[TDE,TDA] != '00' then AArch64_AArch32SystemAccessTrap(EL2, 0x05); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HDCR().[TDE,TDA] != '00' then AArch32_TakeHypTrapException(0x05); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3().TDA == '1' then if EL3SDDUndef() then Undefined(); else AArch64_AArch32SystemAccessTrap(EL3, 0x05); end; elsif DBGOSLSR().OSLK == '0' && HaltingAllowed() && EDSCR().TDA == '1' then Halt(DebugHalt_SoftwareAccess); else DBGBVR(m) = R(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3().TDA == '1' then Undefined(); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3().TDA == '1' then if EL3SDDUndef() then Undefined(); else AArch64_AArch32SystemAccessTrap(EL3, 0x05); end; elsif DBGOSLSR().OSLK == '0' && HaltingAllowed() && EDSCR().TDA == '1' then Halt(DebugHalt_SoftwareAccess); else DBGBVR(m) = R(t); end; elsif PSTATE.EL == EL3 then if DBGOSLSR().OSLK == '0' && HaltingAllowed() && EDSCR().TDA == '1' then Halt(DebugHalt_SoftwareAccess); else DBGBVR(m) = R(t); end; end; 2026-03-26 20:27:25 2026-03_rel