DBGDEVID Debug Device ID register 0 when FEAT_AA32EL1 is implemented Adds to the information given by the DBGDIDR by describing other features of the debug implementation. Identification Registers This register is required in all implementations. DBGDEVID is a 32-bit register. CIDMask 31 28 31:28 Indicates the level of support for the Context ID matching breakpoint masking capability. All other values are reserved. The value of this for Armv8 is 0b0000. 0b0000 Context ID masking is not implemented. 0b0001 Context ID masking is implemented. RO AuxRegs 27 24 27:24 Indicates support for Auxiliary registers. All other values are reserved. 0b0000 None supported. 0b0001 Support for External Debug Auxiliary Control Register, EDACR. RO DoubleLock 23 20 23:20 OS Double Lock implemented. FEAT_DoubleLock implements the functionality identified by the value 0b0001. All other values are reserved. 0b0000 OS Double Lock is not implemented. DBGOSDLR is RAZ/WI. 0b0001 OS Double Lock is implemented. DBGOSDLR is RW. RO VirtExtns 19 16 19:16 Indicates whether EL2 is implemented. All other values are reserved. 0b0000 EL2 is not implemented. 0b0001 EL2 is implemented. RO VectorCatch 15 12 15:12 Defines the form of Vector Catch exception implemented. All other values are reserved. 0b0000 Address matching Vector Catch exception implemented. 0b0001 Exception matching Vector Catch exception implemented. RO BPAddrMask 11 8 11:8 Indicates the level of support for the instruction address matching breakpoint masking capability. All other values are reserved. The value of this for Armv8 is 0b1111. 0b0000 Breakpoint address masking might be implemented. If not implemented, DBGBCR<n>[28:24] is RAZ/WI. 0b0001 Breakpoint address masking is implemented. 0b1111 Breakpoint address masking is not implemented. DBGBCR<n>[28:24] is RES0. RO WPAddrMask 7 4 7:4 Indicates the level of support for the data address matching watchpoint masking capability. All other values are reserved. The value of this for Armv8 is 0b0001. 0b0000 Watchpoint address masking might be implemented. If not implemented, DBGWCR<n>.MASK (Address mask) is RAZ/WI. 0b0001 Watchpoint address masking is implemented. 0b1111 Watchpoint address masking is not implemented. DBGWCR<n>.MASK (Address mask) is RES0. RO PCSample 3 0 3:0 Indicates the level of PC Sample-based Profiling support using external debug registers. All other values are reserved. When FEAT_PCSRv8p2 is implemented, the only permitted value is 0b0000. FEAT_PCSRv8p2 implements the PC Sample-based Profiling Extension in the Performance Monitors register space, as indicated by the value of PMDEVID.PCSample. 0b0000 PC Sample-based Profiling Extension is not implemented in the external debug registers space. 0b0010 Only EDPCSR and EDCIDSR are implemented. This option is only permitted if EL3 and EL2 are not implemented. 0b0011 EDPCSR, EDCIDSR, and EDVIDSR are implemented. RO MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>} if !IsFeatureImplemented(FEAT_AA32EL1) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3().TDA == '1' then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && MDCR_EL2().[TDE,TDA] != '00' then AArch64_AArch32SystemAccessTrap(EL2, 0x05); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HDCR().[TDE,TDA] != '00' then AArch32_TakeHypTrapException(0x05); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3().TDA == '1' then if EL3SDDUndef() then Undefined(); else AArch64_AArch32SystemAccessTrap(EL3, 0x05); end; else R(t) = DBGDEVID(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3().TDA == '1' then Undefined(); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3().TDA == '1' then if EL3SDDUndef() then Undefined(); else AArch64_AArch32SystemAccessTrap(EL3, 0x05); end; else R(t) = DBGDEVID(); end; elsif PSTATE.EL == EL3 then R(t) = DBGDEVID(); end; 2026-03-26 20:27:25 2026-03_rel