DBGDIDR Debug ID Register when FEAT_AA32 is implemented Specifies which version of the Debug architecture is implemented, and some features of the debug implementation. Identification Registers If EL1 cannot use AArch32 then the implementation of this register is OPTIONAL and deprecated. DBGDIDR is a 32-bit register. WRPs 31 28 31:28 Number of watchpoints, minus 1. If FEAT_Debugv8p9 is implemented and 16 or more watchpoints are implemented, this field reads as 0b1111. If AArch32 is supported at EL1, then the PE does not implement more than 16 watchpoints.The value 0b0000 is reserved. 0b0001..0b1111 The number of watchpoints, minus 1. RO BRPs 27 24 27:24 Number of breakpoints, minus 1. If FEAT_Debugv8p9 is implemented and 16 or more breakpoints are implemented, this field reads as 0b1111. If AArch32 is supported at EL1, then the PE does not implement more than 16 breakpoints.The value 0b0000 is reserved. 0b0001..0b1111 The number of breakpoints, minus 1. RO CTX_CMPs 23 20 23:20 Number of context-aware breakpoints, minus 1. The value of this field is never greater than DBGDIDR.BRPs. If FEAT_Debugv8p9 is implemented and 16 or more context-aware breakpoints are implemented, this field reads as 0b1111. If AArch32 is supported at EL1, then the PE does not implement more than 16 breakpoints. 0b0000..0b1111 The number of context-aware breakpoints, minus 1. RO Version 19 16 19:16 Debug architecture version. Indicates presence of Armv8 debug architecture. All other values are reserved. From Armv8.0, the values 0b0000, 0b0001, 0b0010, 0b0011, 0b0100, and 0b0101 are not permitted. FEAT_Debugv8p1 implements the functionality identified by the value 0b0111. FEAT_Debugv8p2 implements the functionality identified by the value 0b1000. FEAT_Debugv8p4 implements the functionality identified by the value 0b1001. FEAT_Debugv8p8 implements the functionality identified by the value 0b1010. FEAT_Debugv8p9 implements the functionality identified by the value 0b1011. From Armv8.1, when FEAT_Debugv8p1 is implemented the value 0b0110 is not permitted. From Armv8.2, the values 0b0110 and 0b0111 are not permitted. From Armv8.4, the value 0b1000 is not permitted. From Armv8.8, the value 0b1001 is not permitted. From Armv8.9, the value 0b1010 is not permitted. 0b0000 Not supported. 0b0001 Armv6, v6 Debug architecture, with System registers access. 0b0010 Armv6, v6.1 Debug architecture, with System registers access. 0b0011 Armv7, v7 Debug architecture, with only baseline System registers. 0b0100 Armv7, v7 Debug architecture, with all System registers implemented. 0b0101 Armv7, v7.1 Debug architecture, with System registers access. 0b0110 Armv8.0 debug architecture. 0b0111 Armv8.1 debug architecture, FEAT_Debugv8p1. 0b1000 Armv8.2 debug architecture, FEAT_Debugv8p2. 0b1001 Armv8.4 debug architecture, FEAT_Debugv8p4. 0b1010 Armv8.8 debug architecture, FEAT_Debugv8p8. 0b1011 Armv8.9 debug architecture, FEAT_Debugv8p9. RO 15 15 15 Reserved, RES1. nSUHD_imp 14 14 14 Previously indicated that Secure User Halting Debug is not implemented. The value of this field must match the value of the SE_imp field. This field has an IMPLEMENTATION DEFINED value. RO 13 13 13 Reserved, RES0. SE_imp 12 12 12 EL3 implemented. The value of this field must match the value of the nSUHD_imp field. 0b0 EL3 not implemented. 0b1 EL3 implemented. RO 11 0 11:0 Reserved, RES0. Arm deprecates any access to this register from EL0. MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>} if !IsFeatureImplemented(FEAT_AA32) then Undefined(); elsif Halted() && ConstrainUnpredictableBool(Unpredictable_IGNORETRAPINDEBUG) then R(t) = DBGDIDR(); elsif PSTATE.EL == EL0 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3().TDA == '1' then Undefined(); elsif IsFeatureImplemented(FEAT_AA64EL1) && !ELUsingAArch32(EL1) && MDSCR_EL1().TDCC == '1' then if EL2Enabled() && (IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2)) && HCR_EL2().TGE == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x05); else AArch64_AArch32SystemAccessTrap(EL1, 0x05); end; elsif IsFeatureImplemented(FEAT_AA32EL1) && ELUsingAArch32(EL1) && DBGDSCRext().UDCCdis == '1' then if EL2Enabled() && (IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2)) && HCR_EL2().TGE == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x05); elsif EL2Enabled() && (IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2)) && HCR().TGE == '1' then AArch32_TakeHypTrapException(0x00); else Undefined(); end; elsif EL2Enabled() && (IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2)) && (HCR_EL2().TGE == '1' || MDCR_EL2().[TDE,TDA] != '00') then AArch64_AArch32SystemAccessTrap(EL2, 0x05); elsif EL2Enabled() && (IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2)) && (HCR().TGE == '1' || HDCR().[TDE,TDA] != '00') then AArch32_TakeHypTrapException(0x05); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3().TDA == '1' then if EL3SDDUndef() then Undefined(); else AArch64_AArch32SystemAccessTrap(EL3, 0x05); end; else R(t) = DBGDIDR(); end; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3().TDA == '1' then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && MDCR_EL2().[TDE,TDA] != '00' then AArch64_AArch32SystemAccessTrap(EL2, 0x05); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HDCR().[TDE,TDA] != '00' then AArch32_TakeHypTrapException(0x05); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3().TDA == '1' then if EL3SDDUndef() then Undefined(); else AArch64_AArch32SystemAccessTrap(EL3, 0x05); end; else R(t) = DBGDIDR(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3().TDA == '1' then Undefined(); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3().TDA == '1' then if EL3SDDUndef() then Undefined(); else AArch64_AArch32SystemAccessTrap(EL3, 0x05); end; else R(t) = DBGDIDR(); end; elsif PSTATE.EL == EL3 then R(t) = DBGDIDR(); end; 2026-03-26 20:27:25 2026-03_rel