DBGDSCRext Debug Status and Control Register, External View when FEAT_AA32EL1 is implemented MDSCR_EL1 Architectural AArch64 31 0 31 0 31 0 31 0 EDSCR Architectural External 31 6 31 6 31 29 27 26 23 21 19 19 14 14 6 6 31 29 27 26 23 21 19 19 14 14 6 6 DBGDSCRint Architectural AArch32 15 15 15 15 15 15 15 15 DBGDSCRint Architectural AArch32 12 12 12 12 12 12 12 12 DBGDSCRint Architectural AArch32 5 2 5 2 5 2 5 2 Main control register for the debug implementation. Debug This register is required in all implementations. DBGDSCRext is a 32-bit register. TFO 31 31 0 Trace Filter override. Used for save/restore of EDSCR.TFO. When the OS Lock is unlocked, DBGOSLSR.OSLK == 0, software must treat this bit as UNK/SBZP. When the OS Lock is locked, DBGOSLSR.OSLK == 1, this bit holds the value of EDSCR.TFO. Reads and writes of this bit are indirect accesses to EDSCR.TFO. '0' When DBGOSLSR.OSLK == '1' RW When DBGOSLSR.OSLK == '0' RO When FEAT_TRF is implemented 31 31 31 Reserved, RES0. Otherwise RXfull 30 30 30 DTRRX full. Used for save/restore of EDSCR.RXfull. When DBGOSLSR.OSLK == 0, software must treat this bit as UNK/SBZP. When DBGOSLSR.OSLK == 1, this bit holds the value of EDSCR.RXfull. Reads and writes of this bit are indirect accesses to EDSCR.RXfull. Arm deprecates use of this bit other than for save/restore. Use DBGDSCRint to access the DTRRX full status. '0' When DBGOSLSR.OSLK == '1' RW When DBGOSLSR.OSLK == '0' RO TXfull 29 29 29 DTRTX full. Used for save/restore of EDSCR.TXfull. When DBGOSLSR.OSLK == 0, software must treat this bit as UNK/SBZP. When DBGOSLSR.OSLK == 1, this bit holds the value of EDSCR.TXfull. Reads and writes of this bit are indirect accesses to EDSCR.TXfull. Arm deprecates use of this bit other than for save/restore. Use DBGDSCRint to access the DTRTX full status. '0' When DBGOSLSR.OSLK == '1' RW When DBGOSLSR.OSLK == '0' RO 28 28 28 Reserved, RES0. RXO 27 27 27 Used for save/restore of EDSCR.RXO. When DBGOSLSR.OSLK == 0, software must treat this bit as UNK/SBZP. When DBGOSLSR.OSLK == 1, this bit holds the value of EDSCR.RXO. Reads and writes of this bit are indirect accesses to EDSCR.RXO. When DBGOSLSR.OSLK == 1, if bits [27,6] of the value written to DBGDSCRext are {1,0}, that is, the RXO bit is 1 and the ERR bit is 0, the PE sets EDSCR.{RXO,ERR} to UNKNOWN values. '0' When DBGOSLSR.OSLK == '1' RW When DBGOSLSR.OSLK == '0' RO TXU 26 26 26 Used for save/restore of EDSCR.TXU. When DBGOSLSR.OSLK == 0, software must treat this bit as UNK/SBZP. When DBGOSLSR.OSLK == 1, this bit holds the value of EDSCR.TXU. Reads and writes of this bit are indirect accesses to EDSCR.TXU. When DBGOSLSR.OSLK == 1, if bits [26,6] of the value written to DBGDSCRext are {1,0}, that is, the TXU bit is 1 and the ERR bit is 0, the PE sets EDSCR.{TXU,ERR} to UNKNOWN values. '0' When DBGOSLSR.OSLK == '1' RW When DBGOSLSR.OSLK == '0' RO 25 24 25:24 Reserved, RES0. INTdis 23 22 23:22 Used for save/restore of EDSCR.INTdis. When DBGOSLSR.OSLK == 0, software must treat it as UNK/SBZP. When DBGOSLSR.OSLK == 1, this field holds the value of EDSCR.INTdis. Reads and writes of this field are indirect accesses to EDSCR.INTdis. '00' When DBGOSLSR.OSLK == '1' RW When DBGOSLSR.OSLK == '0' RO TDA 21 21 21 Used for save/restore of EDSCR.TDA. When DBGOSLSR.OSLK == 0, software must treat this bit as UNK/SBZP. When DBGOSLSR.OSLK == 1, this bit holds the value of EDSCR.TDA. Reads and writes of this bit are indirect accesses to EDSCR.TDA. '0' When DBGOSLSR.OSLK == '1' RW When DBGOSLSR.OSLK == '0' RO 20 20 20 Reserved, RES0. SC2 19 19 0 Used for save/restore of EDSCR.SC2. When DBGOSLSR.OSLK == 0, software must treat this bit as UNK/SBZP. When DBGOSLSR.OSLK == 1, this bit holds the value of EDSCR.SC2. Reads and writes of this bit are indirect accesses to EDSCR.SC2. '0' When DBGOSLSR.OSLK == '1' RW When DBGOSLSR.OSLK == '0' RO When FEAT_PCSRv8 is implemented, FEAT_VHE is implemented, and FEAT_PCSRv8p2 is not implemented 19 19 19 Reserved, RES0. Otherwise NS 18 18 18 Non-secure status. Arm deprecates use of this field. 0b0 Secure state. 0b1 Non-secure state. RO SPNIDdis 17 17 0 Secure privileged profiling disabled status bit. This field reads as 0 if any of the following applies, and reads as 1 otherwise: FEAT_Debugv8p2 is not implemented and ExternalSecureNoninvasiveDebugEnabled() returns TRUE. EL3 is using AArch32 and the value of SDCR.SPME is 1. EL3 is using AArch64 and the value of MDCR_EL3.SPME is 1. Arm deprecates use of this field. 0b0 Profiling allowed in Secure privileged modes. 0b1 Profiling prohibited in Secure privileged modes. RO When EL3 is implemented 17 17 17 Reserved, RES0. Otherwise SPIDdis 16 16 0 Secure privileged AArch32 invasive self-hosted debug disabled status bit. The value of this bit depends on the value of SDCR.SPD and the pseudocode function AArch32.SelfHostedSecurePrivilegedInvasiveDebugEnabled(). This bit reads as 1 if any of the following is true and reads as 0 otherwise: EL3 is using AArch32 and SDCR.SPD has the value 0b10. EL3 is using AArch64 and MDCR_EL3.SPD32 has the value 0b10. EL3 is using AArch32, SDCR.SPD has the value 0b00, and AArch32.SelfHostedSecurePrivilegedInvasiveDebugEnabled() returns FALSE. EL3 is using AArch64, MDCR_EL3.SPD32 has the value 0b00, and AArch32.SelfHostedSecurePrivilegedInvasiveDebugEnabled() returns FALSE. Arm deprecates use of this field. 0b0 Self-hosted debug enabled in Secure privileged AArch32 modes. 0b1 Self-hosted debug disabled in Secure privileged AArch32 modes. RO When EL3 is implemented 16 16 16 Reserved, RES0. Otherwise MDBGen 15 15 15 Monitor debug events enable. Enable Breakpoint, Watchpoint, and Vector Catch exceptions. 0b0 Breakpoint, Watchpoint, and Vector Catch exceptions disabled. 0b1 Breakpoint, Watchpoint, and Vector Catch exceptions enabled. '0' HDE 14 14 14 Used for save/restore of EDSCR.HDE. When DBGOSLSR.OSLK == 0, software must treat this bit as UNK/SBZP. When DBGOSLSR.OSLK == 1, this bit holds the value of EDSCR.HDE. Reads and writes of this bit are indirect accesses to EDSCR.HDE. '0' When DBGOSLSR.OSLK == '1' RW When DBGOSLSR.OSLK == '0' RO 13 13 13 Reserved, RES0. UDCCdis 12 12 12 Traps EL0 accesses to the DCC registers to Undefined mode. All accesses to these registers are trapped, including LDC and STC accesses to DBGDTRTXint and DBGDTRRXint, and MRRC accesses to DBGDSAR and DBGDRAR. Traps of EL0 accesses to the DBGDTRRXint and DBGDTRTXint are ignored in Debug state. 0b0 This control does not cause any instructions to be trapped. 0b1 EL0 accesses to the DBGDSCRint, DBGDTRRXint, DBGDTRTXint, DBGDIDR, DBGDSAR, and DBGDRAR are trapped to Undefined mode. '0' 11 7 11:7 Reserved, RES0. ERR 6 6 6 Used for save/restore of EDSCR.ERR. When DBGOSLSR.OSLK == 0, software must treat this bit as UNK/SBZP. When DBGOSLSR.OSLK == 1, this bit holds the value of EDSCR.ERR. Reads and writes of this bit are indirect accesses to EDSCR.ERR. '0' When DBGOSLSR.OSLK == '1' RW When DBGOSLSR.OSLK == '0' RO MOE 5 2 5:2 Method of Entry for debug exception. When a debug exception is taken to an Exception level using AArch32, this field is set to indicate the event that caused the exception: 0b0001 Breakpoint. 0b0011 Software breakpoint (BKPT) instruction. 0b0101 Vector catch. 0b1010 Watchpoint. AU 1 0 1:0 Reserved, RES0. Individual fields within this register might have restricted accessibility when the OS Lock is unlocked, DBGOSLSR.OSLK == 0. See the field descriptions for more detail. MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>} if !IsFeatureImplemented(FEAT_AA32EL1) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3().TDA == '1' then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && MDCR_EL2().[TDE,TDA] != '00' then AArch64_AArch32SystemAccessTrap(EL2, 0x05); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HDCR().[TDE,TDA] != '00' then AArch32_TakeHypTrapException(0x05); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3().TDA == '1' then if EL3SDDUndef() then Undefined(); else AArch64_AArch32SystemAccessTrap(EL3, 0x05); end; else R(t) = DBGDSCRext(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3().TDA == '1' then Undefined(); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3().TDA == '1' then if EL3SDDUndef() then Undefined(); else AArch64_AArch32SystemAccessTrap(EL3, 0x05); end; else R(t) = DBGDSCRext(); end; elsif PSTATE.EL == EL3 then R(t) = DBGDSCRext(); end; MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>} if !IsFeatureImplemented(FEAT_AA32EL1) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3().TDA == '1' then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && MDCR_EL2().[TDE,TDA] != '00' then AArch64_AArch32SystemAccessTrap(EL2, 0x05); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HDCR().[TDE,TDA] != '00' then AArch32_TakeHypTrapException(0x05); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3().TDA == '1' then if EL3SDDUndef() then Undefined(); else AArch64_AArch32SystemAccessTrap(EL3, 0x05); end; else DBGDSCRext() = R(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3().TDA == '1' then Undefined(); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3().TDA == '1' then if EL3SDDUndef() then Undefined(); else AArch64_AArch32SystemAccessTrap(EL3, 0x05); end; else DBGDSCRext() = R(t); end; elsif PSTATE.EL == EL3 then DBGDSCRext() = R(t); end; 2026-03-26 20:27:25 2026-03_rel