DBGDSCRint Debug Status and Control Register, Internal View when FEAT_AA32 is implemented MDCCSR_EL0 Architectural AArch64 30 29 30 29 30 29 30 29 EDSCR Architectural External 30 29 30 29 30 29 30 29 MDSCR_EL1 Architectural AArch64 15 15 15 15 15 15 15 15 MDSCR_EL1 Architectural AArch64 12 12 12 12 12 12 12 12 MDSCR_EL1 Architectural AArch64 5 2 5 2 5 2 5 2 DBGDSCRext Architectural AArch32 15 15 15 15 15 15 15 15 DBGDSCRext Architectural AArch32 12 12 12 12 12 12 12 12 DBGDSCRext Architectural AArch32 5 2 5 2 5 2 5 2 Main control register for the debug implementation. This is an internal, read-only view. Debug This register is required in all implementations. DBGDSCRint.{NS, SPNIDdis, SPIDdis, MDBGen, UDCCdis, MOE} are UNKNOWN when the register is accessed at EL0. However, although these values are not accessible at EL0 by instructions that are neither UNPREDICTABLE nor return UNKNOWN values, it is permissible for an implementation to return the values of DBGDSCRext.{NS, SPNIDdis, SPIDdis, MDBGen, UDCCdis, MOE} for these fields at EL0. It is also permissible for an implementation to return the same values as defined for a read of DBGDSCRint at EL1 or above. (This is the case even if the implementation does not support AArch32 at EL1 or above.) DBGDSCRint is a 32-bit register. 31 31 31 Reserved, RES0. RXfull 30 30 30 DTRRX full. Read-only view of the equivalent bit in the EDSCR. TXfull 29 29 29 DTRTX full. Read-only view of the equivalent bit in the EDSCR. 28 19 28:19 Reserved, RES0. NS 18 18 18 Non-secure status. Read-only view of the equivalent bit in the DBGDSCRext. Arm deprecates use of this field. SPNIDdis 17 17 17 Secure privileged non-invasive debug disable. Read-only view of the equivalent bit in the DBGDSCRext. Arm deprecates use of this field. SPIDdis 16 16 16 Secure privileged invasive debug disable. Read-only view of the equivalent bit in the DBGDSCRext. Arm deprecates use of this field. MDBGen 15 15 15 Monitor debug events enable. Read-only view of the equivalent bit in the DBGDSCRext. 14 13 14:13 Reserved, RES0. UDCCdis 12 12 12 User mode access to Debug Communications Channel disable. Read-only view of the equivalent bit in the DBGDSCRext. Arm deprecates use of this field. 11 6 11:6 Reserved, RES0. MOE 5 2 5:2 Method of Entry for debug exception. When a debug exception is taken to an Exception level using AArch32, this field is set to indicate the event that caused the exception: Read-only view of the equivalent bit in the DBGDSCRext. 0b0001 Breakpoint 0b0011 Software breakpoint (BKPT) instruction 0b0101 Vector catch 0b1010 Watchpoint 1 0 1:0 Reserved, RES0. When <Rt> is APSR_nzcv, encoded as R15, then instead of reading the entire register, the access copies DBGDSCRint[31:28] into the PSTATE NZCV flags. MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>} if !IsFeatureImplemented(FEAT_AA32) then Undefined(); elsif Halted() && ConstrainUnpredictableBool(Unpredictable_IGNORETRAPINDEBUG) then if t == 15 then ConstrainUnpredictableProcedure(Unpredictable_MRC_APSR_TARGET); else R(t) = DBGDSCRint(); end; elsif PSTATE.EL == EL0 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && IsFeatureImplemented(FEAT_FGT) && MDCR_EL3().TDCC == '1' then Undefined(); elsif HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) && SDCR().TDCC == '1' then Undefined(); elsif HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3().TDA == '1' then Undefined(); elsif IsFeatureImplemented(FEAT_AA64EL1) && !ELUsingAArch32(EL1) && MDSCR_EL1().TDCC == '1' then if EL2Enabled() && (IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2)) && HCR_EL2().TGE == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x05); else AArch64_AArch32SystemAccessTrap(EL1, 0x05); end; elsif IsFeatureImplemented(FEAT_AA32EL1) && ELUsingAArch32(EL1) && DBGDSCRext().UDCCdis == '1' then if EL2Enabled() && (IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2)) && HCR_EL2().TGE == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x05); elsif EL2Enabled() && (IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2)) && HCR().TGE == '1' then AArch32_TakeHypTrapException(0x00); else Undefined(); end; elsif EL2Enabled() && (IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2)) && IsFeatureImplemented(FEAT_FGT) && MDCR_EL2().TDCC == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x05); elsif EL2Enabled() && (IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2)) && IsFeatureImplemented(FEAT_FGT) && HDCR().TDCC == '1' then AArch32_TakeHypTrapException(0x05); elsif EL2Enabled() && (IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2)) && (HCR_EL2().TGE == '1' || MDCR_EL2().[TDE,TDA] != '00') then AArch64_AArch32SystemAccessTrap(EL2, 0x05); elsif EL2Enabled() && (IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2)) && (HCR().TGE == '1' || HDCR().[TDE,TDA] != '00') then AArch32_TakeHypTrapException(0x05); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && IsFeatureImplemented(FEAT_FGT) && MDCR_EL3().TDCC == '1' then if EL3SDDUndef() then Undefined(); else AArch64_AArch32SystemAccessTrap(EL3, 0x05); end; elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) && SDCR().TDCC == '1' then if EL3SDDUndef() then Undefined(); else AArch32_TakeMonitorTrapException(); end; elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3().TDA == '1' then if EL3SDDUndef() then Undefined(); else AArch64_AArch32SystemAccessTrap(EL3, 0x05); end; else if t == 15 then if Halted() then ConstrainUnpredictableProcedure(Unpredictable_MRC_APSR_TARGET); else PSTATE.[N,Z,C,V] = DBGDSCRint()[31:28]; end; else R(t) = DBGDSCRint(); end; end; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && IsFeatureImplemented(FEAT_FGT) && MDCR_EL3().TDCC == '1' then Undefined(); elsif HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) && SDCR().TDCC == '1' then Undefined(); elsif HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3().TDA == '1' then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && IsFeatureImplemented(FEAT_FGT) && MDCR_EL2().TDCC == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x05); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HDCR().TDCC == '1' then AArch32_TakeHypTrapException(0x05); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && MDCR_EL2().[TDE,TDA] != '00' then AArch64_AArch32SystemAccessTrap(EL2, 0x05); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HDCR().[TDE,TDA] != '00' then AArch32_TakeHypTrapException(0x05); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && IsFeatureImplemented(FEAT_FGT) && MDCR_EL3().TDCC == '1' then if EL3SDDUndef() then Undefined(); else AArch64_AArch32SystemAccessTrap(EL3, 0x05); end; elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) && SDCR().TDCC == '1' then if EL3SDDUndef() then Undefined(); else AArch32_TakeMonitorTrapException(); end; elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3().TDA == '1' then if EL3SDDUndef() then Undefined(); else AArch64_AArch32SystemAccessTrap(EL3, 0x05); end; else if t == 15 then if Halted() then ConstrainUnpredictableProcedure(Unpredictable_MRC_APSR_TARGET); else PSTATE.[N,Z,C,V] = DBGDSCRint()[31:28]; end; else R(t) = DBGDSCRint(); end; end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && IsFeatureImplemented(FEAT_FGT) && MDCR_EL3().TDCC == '1' then Undefined(); elsif HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) && SDCR().TDCC == '1' then Undefined(); elsif HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3().TDA == '1' then Undefined(); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && IsFeatureImplemented(FEAT_FGT) && MDCR_EL3().TDCC == '1' then if EL3SDDUndef() then Undefined(); else AArch64_AArch32SystemAccessTrap(EL3, 0x05); end; elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) && SDCR().TDCC == '1' then if EL3SDDUndef() then Undefined(); else AArch32_TakeMonitorTrapException(); end; elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3().TDA == '1' then if EL3SDDUndef() then Undefined(); else AArch64_AArch32SystemAccessTrap(EL3, 0x05); end; else if t == 15 then if Halted() then ConstrainUnpredictableProcedure(Unpredictable_MRC_APSR_TARGET); else PSTATE.[N,Z,C,V] = DBGDSCRint()[31:28]; end; else R(t) = DBGDSCRint(); end; end; elsif PSTATE.EL == EL3 then if PSTATE.M != M32_Monitor && SDCR().TDCC == '1' then AArch32_TakeMonitorTrapException(); else if t == 15 then if Halted() then ConstrainUnpredictableProcedure(Unpredictable_MRC_APSR_TARGET); else PSTATE.[N,Z,C,V] = DBGDSCRint()[31:28]; end; else R(t) = DBGDSCRint(); end; end; end; 2026-03-26 20:27:25 2026-03_rel