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<!DOCTYPE register_page SYSTEM "registers.dtd">
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<register_page>
  <registers>
  
    <register execution_state="AArch32" is_register="True" is_internal="True" is_stub_entry="False">
      <reg_short_name>DBGOSECCR</reg_short_name>
        
        <reg_long_name>Debug OS Lock Exception Catch Control Register</reg_long_name>



      
            <reg_condition otherwise="UNDEFINED">when FEAT_AA32EL1 is implemented</reg_condition>
      




          <reg_reset_value></reg_reset_value>

      <reg_mappings>
        



    
      
      <reg_mapping>
        
  

    

  

    <mapped_name filename="AArch64-oseccr_el1.xml">OSECCR_EL1</mapped_name>
  <mapped_type>Architectural</mapped_type>
      <mapped_execution_state>AArch64</mapped_execution_state>
    <mapped_from_startbit>31</mapped_from_startbit>
    <mapped_from_endbit>0</mapped_from_endbit>
    <mapped_to_startbit>31</mapped_to_startbit>
    <mapped_to_endbit>0</mapped_to_endbit>
    <mapped_from_rangeset output="31:0">
      <range>
        <msb>31</msb>
        <lsb>0</lsb>
      </range>
    </mapped_from_rangeset>
    <mapped_to_rangeset output="31:0">
      <range>
        <msb>31</msb>
        <lsb>0</lsb>
      </range>
    </mapped_to_rangeset>

      </reg_mapping>
    
      
      <reg_mapping>
        
  

    

  

    <mapped_name filename="ext-edeccr.xml">EDECCR</mapped_name>
  <mapped_type>Architectural</mapped_type>
      <mapped_execution_state>External</mapped_execution_state>
    <mapped_from_startbit>31</mapped_from_startbit>
    <mapped_from_endbit>0</mapped_from_endbit>
    <mapped_to_startbit>31</mapped_to_startbit>
    <mapped_to_endbit>0</mapped_to_endbit>
    <mapped_from_rangeset output="31:0">
      <range>
        <msb>31</msb>
        <lsb>0</lsb>
      </range>
    </mapped_from_rangeset>
    <mapped_to_rangeset output="31:0">
      <range>
        <msb>31</msb>
        <lsb>0</lsb>
      </range>
    </mapped_to_rangeset>

      </reg_mapping>

      </reg_mappings>

        <reg_purpose>
          
    
      <purpose_text>
        <para>Provides a mechanism for an operating system to access the contents of <register_link state="ext" id="ext-edeccr.xml">EDECCR</register_link> that are otherwise invisible to software, so it can save/restore the contents of <register_link state="ext" id="ext-edeccr.xml">EDECCR</register_link> over powerdown on behalf of the external debugger.</para>
      </purpose_text>

        </reg_purpose>

      <reg_groups>
          <reg_group>Debug</reg_group>
      </reg_groups>
      <reg_configuration>
        
    
      <configuration_text>
        <para>If <register_link state="AArch32" id="AArch32-dbgoslsr.xml">DBGOSLSR</register_link>.OSLK == 0 then DBGOSECCR returns an <arm-defined-word>UNKNOWN</arm-defined-word> value on reads and ignores writes.</para>
      </configuration_text>

      </reg_configuration>
      
      
        
      <reg_attributes>
          
    
      <attributes_text>
        <para>DBGOSECCR is a 32-bit register.</para>
      </attributes_text>

      </reg_attributes>
      <reg_fieldsets>
        






<fields id="fieldset_0" length="32">
  <fields_condition>When DBGOSLSR.OSLK == '1'</fields_condition>
  <fields_instance>DBGOSLSR.OSLK==1</fields_instance>
  <text_before_fields/>
  <field id="fieldset_0-31_0" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False">
    <field_name>EDECCR</field_name>
    <field_msb>31</field_msb>
    <field_lsb>0</field_lsb>
    <rel_range>31:0</rel_range>
    <field_description order="before"><para>Used for save/restore to <register_link state="ext" id="ext-edeccr.xml">EDECCR</register_link> over powerdown.</para>
<para>Reads or writes to this field are indirect accesses to <register_link state="ext" id="ext-edeccr.xml">EDECCR</register_link>.</para></field_description>
    <field_resets>
      <field_reset reset_type="Cold">
        <field_reset_expression>0x00</field_reset_expression>
      </field_reset>
    </field_resets>
  </field>
  <text_after_fields/>
</fields>




<reg_fieldset length="32">
  <fields_condition>When DBGOSLSR.OSLK == '1'</fields_condition>
  <fieldat id="fieldset_0-31_0" msb="31" lsb="0"/>
</reg_fieldset>


      </reg_fieldsets>

      <access_mechanisms>
          






    
        
        <access_mechanism accessor="MRC DBGOSECCR" type="SystemAccessor">
            <encoding>
            <access_instruction>MRC{&lt;c&gt;}{&lt;q&gt;} &lt;coproc&gt;, {#}&lt;opc1&gt;, &lt;Rt&gt;, &lt;CRn&gt;, &lt;CRm&gt;{, {#}&lt;opc2&gt;}</access_instruction>
                
                <enc n="coproc" v="0b1110"/>
                
                <enc n="opc1" v="0b000"/>
                
                <enc n="CRn" v="0b0000"/>
                
                <enc n="CRm" v="0b0110"/>
                
                <enc n="opc2" v="0b010"/>
            </encoding>
            <access_permission>
                <ps name="MRC" sections="1" secttype="access_permission">
                <pstext>
if !IsFeatureImplemented(FEAT_AA32EL1) then
    Undefined();
elsif PSTATE.EL == EL0 then
    Undefined();
elsif PSTATE.EL == EL1 then
    if HaveEL(EL3) &amp;&amp; EL3SDDUndefPriority() &amp;&amp; IsFeatureImplemented(FEAT_AA64EL3) &amp;&amp; !ELUsingAArch32(EL3) &amp;&amp; MDCR_EL3().TDA == '1' then
        Undefined();
    elsif EL2Enabled() &amp;&amp; IsFeatureImplemented(FEAT_AA64EL2) &amp;&amp; !ELUsingAArch32(EL2) &amp;&amp; MDCR_EL2().[TDE,TDA] != '00' then
        AArch64_AArch32SystemAccessTrap(EL2, 0x05);
    elsif EL2Enabled() &amp;&amp; IsFeatureImplemented(FEAT_AA32EL2) &amp;&amp; ELUsingAArch32(EL2) &amp;&amp; HDCR().[TDE,TDA] != '00' then
        AArch32_TakeHypTrapException(0x05);
    elsif HaveEL(EL3) &amp;&amp; IsFeatureImplemented(FEAT_AA64EL3) &amp;&amp; !ELUsingAArch32(EL3) &amp;&amp; MDCR_EL3().TDA == '1' then
        if EL3SDDUndef() then
            Undefined();
        else
            AArch64_AArch32SystemAccessTrap(EL3, 0x05);
        end;
    elsif DBGOSLSR().OSLK == '0' then
        R(t) = ARBITRARY:bits(32);
    else
        R(t) = DBGOSECCR();
    end;
elsif PSTATE.EL == EL2 then
    if HaveEL(EL3) &amp;&amp; EL3SDDUndefPriority() &amp;&amp; IsFeatureImplemented(FEAT_AA64EL3) &amp;&amp; !ELUsingAArch32(EL3) &amp;&amp; MDCR_EL3().TDA == '1' then
        Undefined();
    elsif HaveEL(EL3) &amp;&amp; IsFeatureImplemented(FEAT_AA64EL3) &amp;&amp; !ELUsingAArch32(EL3) &amp;&amp; MDCR_EL3().TDA == '1' then
        if EL3SDDUndef() then
            Undefined();
        else
            AArch64_AArch32SystemAccessTrap(EL3, 0x05);
        end;
    elsif DBGOSLSR().OSLK == '0' then
        R(t) = ARBITRARY:bits(32);
    else
        R(t) = DBGOSECCR();
    end;
elsif PSTATE.EL == EL3 then
    if DBGOSLSR().OSLK == '0' then
        R(t) = ARBITRARY:bits(32);
    else
        R(t) = DBGOSECCR();
    end;
end;
                </pstext>
                </ps>
            </access_permission>
        </access_mechanism>
    
        
        <access_mechanism accessor="MCR DBGOSECCR" type="SystemAccessor">
            <encoding>
            <access_instruction>MCR{&lt;c&gt;}{&lt;q&gt;} &lt;coproc&gt;, {#}&lt;opc1&gt;, &lt;Rt&gt;, &lt;CRn&gt;, &lt;CRm&gt;{, {#}&lt;opc2&gt;}</access_instruction>
                
                <enc n="coproc" v="0b1110"/>
                
                <enc n="opc1" v="0b000"/>
                
                <enc n="CRn" v="0b0000"/>
                
                <enc n="CRm" v="0b0110"/>
                
                <enc n="opc2" v="0b010"/>
            </encoding>
            <access_permission>
                <ps name="MCR" sections="1" secttype="access_permission">
                <pstext>
if !IsFeatureImplemented(FEAT_AA32EL1) then
    Undefined();
elsif PSTATE.EL == EL0 then
    Undefined();
elsif PSTATE.EL == EL1 then
    if HaveEL(EL3) &amp;&amp; EL3SDDUndefPriority() &amp;&amp; IsFeatureImplemented(FEAT_AA64EL3) &amp;&amp; !ELUsingAArch32(EL3) &amp;&amp; MDCR_EL3().TDA == '1' then
        Undefined();
    elsif EL2Enabled() &amp;&amp; IsFeatureImplemented(FEAT_AA64EL2) &amp;&amp; !ELUsingAArch32(EL2) &amp;&amp; MDCR_EL2().[TDE,TDA] != '00' then
        AArch64_AArch32SystemAccessTrap(EL2, 0x05);
    elsif EL2Enabled() &amp;&amp; IsFeatureImplemented(FEAT_AA32EL2) &amp;&amp; ELUsingAArch32(EL2) &amp;&amp; HDCR().[TDE,TDA] != '00' then
        AArch32_TakeHypTrapException(0x05);
    elsif HaveEL(EL3) &amp;&amp; IsFeatureImplemented(FEAT_AA64EL3) &amp;&amp; !ELUsingAArch32(EL3) &amp;&amp; MDCR_EL3().TDA == '1' then
        if EL3SDDUndef() then
            Undefined();
        else
            AArch64_AArch32SystemAccessTrap(EL3, 0x05);
        end;
    elsif DBGOSLSR().OSLK == '0' then
        return;
    else
        DBGOSECCR() = R(t);
    end;
elsif PSTATE.EL == EL2 then
    if HaveEL(EL3) &amp;&amp; EL3SDDUndefPriority() &amp;&amp; IsFeatureImplemented(FEAT_AA64EL3) &amp;&amp; !ELUsingAArch32(EL3) &amp;&amp; MDCR_EL3().TDA == '1' then
        Undefined();
    elsif HaveEL(EL3) &amp;&amp; IsFeatureImplemented(FEAT_AA64EL3) &amp;&amp; !ELUsingAArch32(EL3) &amp;&amp; MDCR_EL3().TDA == '1' then
        if EL3SDDUndef() then
            Undefined();
        else
            AArch64_AArch32SystemAccessTrap(EL3, 0x05);
        end;
    elsif DBGOSLSR().OSLK == '0' then
        return;
    else
        DBGOSECCR() = R(t);
    end;
elsif PSTATE.EL == EL3 then
    if DBGOSLSR().OSLK == '0' then
        return;
    else
        DBGOSECCR() = R(t);
    end;
end;
                </pstext>
                </ps>
            </access_permission>
        </access_mechanism>

      </access_mechanisms>

      <arch_variants>
      </arch_variants>
  </register>
</registers>
<timestamp>2026-03-26 20:27:25</timestamp>
<commit_id>2026-03_rel</commit_id>
</register_page>