DBGVCR Debug Vector Catch Register when FEAT_AA32EL1 is implemented DBGVCR32_EL2 Architectural AArch64 31 0 31 0 31 0 31 0 Controls Vector Catch debug events. Debug This register is required in all implementations. DBGVCR is a 32-bit register. When EL3 is implemented and EL3 is using AArch32 EL3 is implemented and using AArch32 NSF 31 31 31 FIQ vector catch enable in Non-secure state. The exception vector offset is 0x1C. AU NSI 30 30 30 IRQ vector catch enable in Non-secure state. The exception vector offset is 0x18. AU 29 29 29 Reserved, RES0. NSD 28 28 28 Data Abort exception vector catch enable in Non-secure state. The exception vector offset is 0x10. AU NSP 27 27 27 Prefetch Abort vector catch enable in Non-secure state. The exception vector offset is 0x0C. AU NSS 26 26 26 Supervisor Call (SVC) vector catch enable in Non-secure state. The exception vector offset is 0x08. AU NSU 25 25 25 Undefined Instruction vector catch enable in Non-secure state. The exception vector offset is 0x04. AU 24 16 24:16 Reserved, RES0. MF 15 15 15 FIQ vector catch enable in Monitor mode. The exception vector offset is 0x1C. AU MI 14 14 14 IRQ vector catch enable in Monitor mode. The exception vector offset is 0x18. AU 13 13 13 Reserved, RES0. MD 12 12 12 Data Abort exception vector catch enable in Monitor mode. The exception vector offset is 0x10. AU MP 11 11 11 Prefetch Abort vector catch enable in Monitor mode. The exception vector offset is 0x0C. AU MS 10 10 10 Secure Monitor Call (SMC) vector catch enable in Monitor mode. The exception vector offset is 0x08. AU 9 8 9:8 Reserved, RES0. SF 7 7 7 FIQ vector catch enable in Secure state. The exception vector offset is 0x1C. AU SI 6 6 6 IRQ vector catch enable in Secure state. The exception vector offset is 0x18. AU 5 5 5 Reserved, RES0. SD 4 4 4 Data Abort exception vector catch enable in Secure state. The exception vector offset is 0x10. AU SP 3 3 3 Prefetch Abort vector catch enable in Secure state. The exception vector offset is 0x0C. AU SS 2 2 2 Supervisor Call (SVC) vector catch enable in Secure state. The exception vector offset is 0x08. AU SU 1 1 1 Undefined Instruction vector catch enable in Secure state. The exception vector offset is 0x04. AU 0 0 0 Reserved, RES0. When EL3 is implemented and EL3 is using AArch64 EL3 is implemented and using AArch64 NSF 31 31 31 FIQ vector catch enable in Non-secure state. The exception vector offset is 0x1C. AU NSI 30 30 30 IRQ vector catch enable in Non-secure state. The exception vector offset is 0x18. AU 29 29 29 Reserved, RES0. NSD 28 28 28 Data Abort exception vector catch enable in Non-secure state. The exception vector offset is 0x10. AU NSP 27 27 27 Prefetch Abort vector catch enable in Non-secure state. The exception vector offset is 0x0C. AU NSS 26 26 26 Supervisor Call (SVC) vector catch enable in Non-secure state. The exception vector offset is 0x08. AU NSU 25 25 25 Undefined Instruction vector catch enable in Non-secure state. The exception vector offset is 0x04. AU 24 8 24:8 Reserved, RES0. SF 7 7 7 FIQ vector catch enable in Secure state. The exception vector offset is 0x1C. AU SI 6 6 6 IRQ vector catch enable in Secure state. The exception vector offset is 0x18. AU 5 5 5 Reserved, RES0. SD 4 4 4 Data Abort exception vector catch enable in Secure state. The exception vector offset is 0x10. AU SP 3 3 3 Prefetch Abort vector catch enable in Secure state. The exception vector offset is 0x0C. AU SS 2 2 2 Supervisor Call (SVC) vector catch enable in Secure state. The exception vector offset is 0x08. AU SU 1 1 1 Undefined Instruction vector catch enable in Secure state. The exception vector offset is 0x04. AU 0 0 0 Reserved, RES0. When EL3 is not implemented EL3 is not implemented 31 8 31:8 Reserved, RES0. F 7 7 7 FIQ vector catch enable. The exception vector offset is 0x1C. AU I 6 6 6 IRQ vector catch enable. The exception vector offset is 0x18. AU 5 5 5 Reserved, RES0. D 4 4 4 Data Abort exception vector catch enable. The exception vector offset is 0x10. AU P 3 3 3 Prefetch Abort vector catch enable. The exception vector offset 0x0C. AU S 2 2 2 Supervisor Call (SVC) vector catch enable. The exception vector offset is 0x08. AU U 1 1 1 Undefined Instruction vector catch enable. The exception vector offset is 0x04. AU 0 0 0 Reserved, RES0. When EL3 is implemented and EL3 is using AArch32 When EL3 is implemented and EL3 is using AArch64 When EL3 is not implemented MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>} if !IsFeatureImplemented(FEAT_AA32EL1) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3().TDA == '1' then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && MDCR_EL2().[TDE,TDA] != '00' then AArch64_AArch32SystemAccessTrap(EL2, 0x05); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HDCR().[TDE,TDA] != '00' then AArch32_TakeHypTrapException(0x05); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3().TDA == '1' then if EL3SDDUndef() then Undefined(); else AArch64_AArch32SystemAccessTrap(EL3, 0x05); end; else R(t) = DBGVCR(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3().TDA == '1' then Undefined(); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3().TDA == '1' then if EL3SDDUndef() then Undefined(); else AArch64_AArch32SystemAccessTrap(EL3, 0x05); end; else R(t) = DBGVCR(); end; elsif PSTATE.EL == EL3 then R(t) = DBGVCR(); end; MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>} if !IsFeatureImplemented(FEAT_AA32EL1) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3().TDA == '1' then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && MDCR_EL2().[TDE,TDA] != '00' then AArch64_AArch32SystemAccessTrap(EL2, 0x05); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HDCR().[TDE,TDA] != '00' then AArch32_TakeHypTrapException(0x05); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3().TDA == '1' then if EL3SDDUndef() then Undefined(); else AArch64_AArch32SystemAccessTrap(EL3, 0x05); end; else DBGVCR() = R(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3().TDA == '1' then Undefined(); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3().TDA == '1' then if EL3SDDUndef() then Undefined(); else AArch64_AArch32SystemAccessTrap(EL3, 0x05); end; else DBGVCR() = R(t); end; elsif PSTATE.EL == EL3 then DBGVCR() = R(t); end; 2026-03-26 20:27:25 2026-03_rel