DBGWCR<n>
Debug Watchpoint Control Registers
when FEAT_AA32EL1 is implemented
0
15
DBGWCR<n>_EL1
Architectural
AArch64
31
0
31
0
31
0
31
0
DBGWCR<n>_EL1
Architectural
External
31
0
31
0
31
0
31
0
Holds control information for a watchpoint. Forms watchpoint n together with value register DBGWVR<n>.
Debug
If watchpoint n is not implemented then accesses to this register are UNDEFINED.
DBGWCR<n> is a 32-bit register.
When the E field is zero, all the other fields in the register are ignored.
31
29
31:29
Reserved, RES0.
MASK
28
24
28:24
Address Mask. Only objects up to 2GB can be watched using a single mask.
All other values are reserved.
Indicates the number of masked address bits, from 0b00011 masking 3 address bits (0x00000007 mask for address) to 0b11111 masking 31 address bits (0x7FFFFFFF mask for address).
If programmed with a reserved value, the watchpoint behaves as if either:
DBGWCR<n>.MASK has been programmed with a defined value, which might be 0 (no mask), other than for a direct read of DBGWCR<n>.
The watchpoint is disabled.
0b00000
No mask.
0b00011..0b11111
Number of address bits masked.
AU
23
21
23:21
Reserved, RES0.
WT
20
20
20
Watchpoint type. Possible values are:
0b0
Unlinked data address match.
0b1
Linked data address match.
AU
LBN
19
16
19:16
Linked Breakpoint Number. For Linked data address watchpoints, this specifies the index of the context-matching breakpoint linked to.
AU
SSC
15
14
15:14
Security state control. Determines the Security states under which a Watchpoint debug event for watchpoint n is generated. This field must be interpreted along with the HMC and PAC fields.
For more information, see 'Execution conditions for which a watchpoint generates Watchpoint exceptions', and 'Reserved DBGWCR<n>.{SSC, HMC, PAC} values'.
AU
HMC
13
13
13
Higher mode control. Determines the debug perspective for deciding when a Watchpoint debug event for watchpoint n is generated. This field must be interpreted along with the SSC and PAC fields.
For more information on the operation of the SSC, HMC, and PAC fields, see 'Execution conditions for which a watchpoint generates Watchpoint exceptions'.
AU
BAS
12
5
12:5
Byte address select. Each bit of this field selects whether a byte from within the word or doubleword addressed by DBGWVR<n> is being watched.
BASDescription
0bxxxxxxx1Match byte at DBGWVR<n>
0bxxxxxx1xMatch byte at DBGWVR<n>+1
0bxxxxx1xxMatch byte at DBGWVR<n>+2
0bxxxx1xxxMatch byte at DBGWVR<n>+3
In cases where DBGWVR<n> addresses a doubleword:
BASDescription, if DBGWVR<n>[2] == 0
0bxxx1xxxxMatch byte at DBGWVR<n>+4
0bxx1xxxxxMatch byte at DBGWVR<n>+5
0bx1xxxxxxMatch byte at DBGWVR<n>+6
0b1xxxxxxxMatch byte at DBGWVR<n>+7
If DBGWVR<n>[2] == 1, only BAS[3:0] are used and BAS[7:4] are ignored. Arm deprecates setting DBGWVR<n>[2] == 1.
The valid values for BAS are nonzero binary numbers all of whose set bits are contiguous. All other values are reserved and must not be used by software. See 'Reserved DBGWCR<n>.BAS values'.
AU
LSC
4
3
4:3
Load/store control. This field enables watchpoint matching on the type of access being made. Possible values of this field are:
All other values are reserved, but must behave as if the watchpoint is disabled. Software must not rely on this property as the behavior of reserved values might change in a future revision of the architecture.
0b01
Match instructions that load from a watchpointed address.
0b10
Match instructions that store to a watchpointed address.
0b11
Match instructions that load from or store to a watchpointed address.
AU
PAC
2
1
2:1
Privilege of access control. Determines the Exception level or levels at which a Watchpoint debug event for watchpoint n is generated. This field must be interpreted along with the SSC and HMC fields.
For more information on the operation of the SSC, HMC, and PAC fields, see 'Execution conditions for which a watchpoint generates Watchpoint exceptions'.
AU
E
0
0
0
Enable watchpoint n. Possible values are:
0b0
Watchpoint disabled.
0b1
Watchpoint enabled.
AU
0-15
MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
let m:integer = UInt(CRm[3:0]);
if !IsFeatureImplemented(FEAT_AA32EL1) then
Undefined();
elsif m >= NUM_WATCHPOINTS then
Undefined();
elsif PSTATE.EL == EL0 then
Undefined();
elsif PSTATE.EL == EL1 then
if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3().TDA == '1' then
Undefined();
elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && MDCR_EL2().[TDE,TDA] != '00' then
AArch64_AArch32SystemAccessTrap(EL2, 0x05);
elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HDCR().[TDE,TDA] != '00' then
AArch32_TakeHypTrapException(0x05);
elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3().TDA == '1' then
if EL3SDDUndef() then
Undefined();
else
AArch64_AArch32SystemAccessTrap(EL3, 0x05);
end;
elsif DBGOSLSR().OSLK == '0' && HaltingAllowed() && EDSCR().TDA == '1' then
Halt(DebugHalt_SoftwareAccess);
else
R(t) = DBGWCR(m);
end;
elsif PSTATE.EL == EL2 then
if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3().TDA == '1' then
Undefined();
elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3().TDA == '1' then
if EL3SDDUndef() then
Undefined();
else
AArch64_AArch32SystemAccessTrap(EL3, 0x05);
end;
elsif DBGOSLSR().OSLK == '0' && HaltingAllowed() && EDSCR().TDA == '1' then
Halt(DebugHalt_SoftwareAccess);
else
R(t) = DBGWCR(m);
end;
elsif PSTATE.EL == EL3 then
if DBGOSLSR().OSLK == '0' && HaltingAllowed() && EDSCR().TDA == '1' then
Halt(DebugHalt_SoftwareAccess);
else
R(t) = DBGWCR(m);
end;
end;
0-15
MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
let m:integer = UInt(CRm[3:0]);
if !IsFeatureImplemented(FEAT_AA32EL1) then
Undefined();
elsif m >= NUM_WATCHPOINTS then
Undefined();
elsif PSTATE.EL == EL0 then
Undefined();
elsif PSTATE.EL == EL1 then
if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3().TDA == '1' then
Undefined();
elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && MDCR_EL2().[TDE,TDA] != '00' then
AArch64_AArch32SystemAccessTrap(EL2, 0x05);
elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HDCR().[TDE,TDA] != '00' then
AArch32_TakeHypTrapException(0x05);
elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3().TDA == '1' then
if EL3SDDUndef() then
Undefined();
else
AArch64_AArch32SystemAccessTrap(EL3, 0x05);
end;
elsif DBGOSLSR().OSLK == '0' && HaltingAllowed() && EDSCR().TDA == '1' then
Halt(DebugHalt_SoftwareAccess);
else
DBGWCR(m) = R(t);
end;
elsif PSTATE.EL == EL2 then
if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3().TDA == '1' then
Undefined();
elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3().TDA == '1' then
if EL3SDDUndef() then
Undefined();
else
AArch64_AArch32SystemAccessTrap(EL3, 0x05);
end;
elsif DBGOSLSR().OSLK == '0' && HaltingAllowed() && EDSCR().TDA == '1' then
Halt(DebugHalt_SoftwareAccess);
else
DBGWCR(m) = R(t);
end;
elsif PSTATE.EL == EL3 then
if DBGOSLSR().OSLK == '0' && HaltingAllowed() && EDSCR().TDA == '1' then
Halt(DebugHalt_SoftwareAccess);
else
DBGWCR(m) = R(t);
end;
end;
2026-03-26 20:27:25
2026-03_rel