DSPSR Debug Saved Program Status Register when FEAT_AA32 is implemented DSPSR_EL0 Architectural AArch64 31 0 31 0 31 0 31 0 Holds the saved process state for Debug state. On entering Debug state, PSTATE information is written to this register. On exiting Debug state, values are copied from this register to PSTATE. Special DSPSR is a 32-bit register. N 31 31 31 Negative Condition flag. Set to the value of PSTATE.N on entering Debug state, and copied to PSTATE.N on exiting Debug state. AU Z 30 30 30 Zero Condition flag. Set to the value of PSTATE.Z on entering Debug state, and copied to PSTATE.Z on exiting Debug state. AU C 29 29 29 Carry Condition flag. Set to the value of PSTATE.C on entering Debug state, and copied to PSTATE.C on exiting Debug state. AU V 28 28 28 Overflow Condition flag. Set to the value of PSTATE.V on entering Debug state, and copied to PSTATE.V on exiting Debug state. AU Q 27 27 27 Overflow or saturation flag. Set to the value of PSTATE.Q on entering Debug state, and copied to PSTATE.Q on exiting Debug state. AU IT 26 25 15:10, 26:25 If-Then. Set to the value of PSTATE.IT on entering Debug state, and copied to PSTATE.IT on exiting Debug state. On exiting Debug state, DSPSR.IT must contain a value that is valid for the instruction being returned to. The IT field is split as follows: IT[1:0] is DSPSR[26:25]. IT[7:2] is DSPSR[15:10]. 15 10 26 25 AU DIT 24 24 0 Data Independent Timing. Set to the value of PSTATE.DIT on entering Debug state, and copied to PSTATE.DIT on exiting Debug state. AU When FEAT_DIT is implemented 24 24 24 Reserved, RES0. Otherwise SSBS 23 23 0 Speculative Store Bypass. Set to the value of PSTATE.SSBS on entering Debug state, and copied to PSTATE.SSBS on exiting Debug state. AU When FEAT_SSBS is implemented 23 23 23 Reserved, RES0. Otherwise PAN 22 22 0 Privileged Access Never. Set to the value of PSTATE.PAN on entering Debug state, and copied to PSTATE.PAN on exiting Debug state. AU When FEAT_PAN is implemented 22 22 22 Reserved, RES0. Otherwise SS 21 21 21 Software Step. Set to the value of PSTATE.SS on entering Debug state, and conditionally copied to PSTATE.SS on exiting Debug state. AU IL 20 20 20 Illegal Execution state. Set to the value of PSTATE.IL on entering Debug state, and copied to PSTATE.IL on exiting Debug state. AU GE 19 16 19:16 Greater than or Equal flags. Set to the value of PSTATE.GE on entering Debug state, and copied to PSTATE.GE on exiting Debug state. AU IT[7:2] 15 10 15:10, 26:25 This field is bits[7:2] of IT[7:0]. See IT[1:0] for the field description. E 9 9 9 Endianness. Set to the value of PSTATE.E on entering Debug state, and copied to PSTATE.E on exiting Debug state. If the implementation does not support big-endian operation, DSPSR.E is RES0. If the implementation does not support little-endian operation, DSPSR.E is RES1. On exiting Debug state, if the implementation does not support big-endian operation at the Exception level being returned to, DSPSR.E is RES0, and if the implementation does not support little-endian operation at the Exception level being returned to, DSPSR.E is RES1. AU A 8 8 8 SError exception mask. Set to the value of PSTATE.A on entering Debug state, and copied to PSTATE.A on exiting Debug state. AU I 7 7 7 IRQ interrupt mask. Set to the value of PSTATE.I on entering Debug state, and copied to PSTATE.I on exiting Debug state. AU F 6 6 6 FIQ interrupt mask. Set to the value of PSTATE.F on entering Debug state, and copied to PSTATE.F on exiting Debug state. AU T 5 5 5 T32 Instruction set state. Set to the value of PSTATE.T on entering Debug state, and copied to PSTATE.T on exiting Debug state. AU M[4:0] 4 0 4:0 Mode. Set to the value of PSTATE.M[4:0] on entering Debug state, and copied to PSTATE.M[4:0] on exiting Debug state. Other values are reserved. If DSPSR.M[4:0] has a Reserved value, or a value for an unimplemented Exception level, exiting Debug state is an illegal return event, as described in 'Illegal return events from AArch32 state'. 0b10000 User. 0b10001 FIQ. 0b10010 IRQ. 0b10011 Supervisor. 0b10110 Monitor. When FEAT_EL3 is implemented 0b10111 Abort. 0b11010 Hyp. When FEAT_EL3 is implemented 0b11011 Undefined. 0b11111 System. AU MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>} if !IsFeatureImplemented(FEAT_AA32) then Undefined(); elsif !Halted() then Undefined(); else R(t) = DSPSR(); end; MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>} if !IsFeatureImplemented(FEAT_AA32) then Undefined(); elsif !Halted() then Undefined(); else DSPSR() = R(t); end; 2026-03-26 20:27:25 2026-03_rel