DTLBIMVA Data TLB Invalidate by VA when FEAT_AA32EL1 is implemented Invalidate all cached copies of translation table entries from data TLBs that meet the following requirements: The entry is a stage 1 translation table entry. The entry would be used to translate the specified address, and one of the following applies: The entry is from a level of lookup above the final level and matches the specified ASID. The entry is a global entry from the final level of lookup. The entry is a non-global entry from the final level of lookup that matches the specified ASID. If EL2 is implemented and enabled in the current Security state, the entry would be used with the current VMID. From the entries that match these requirements, the entries that are invalidated are required for the following translation regime: If executed at Secure EL1 when EL3 is using AArch64, the Secure EL1&0 translation regime. If executed in Secure state when EL3 is using AArch32, the Secure PL1&0 translation regime. If executed in Non-secure state, the Non-secure PL1&0 translation regime. The invalidation only applies to the PE that executes this System instruction. Arm deprecates the use of this System instruction. It is only provided for backward compatibility with earlier versions of the Arm architecture. TLB DTLBIMVA is a 32-bit System instruction. VA 31 12 31:12 Virtual address to match. Any TLB entries that match the ASID value and VA value will be affected by this System instruction. 11 8 11:8 Reserved, RES0. ASID 7 0 7:0 ASID value to match. Any TLB entries that match the ASID value and VA value will be affected by this System instruction. Global TLB entries that match the VA value will be affected by this System instruction, regardless of the value of the ASID field. The following pseudocode describes traps which apply to the System instruction. For information about changes to the scope of the invalidation to the instruction under different conditions, see the relevant instruction in the Pseudocode for AArch32 operation. MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>} if !IsFeatureImplemented(FEAT_AA32EL1) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T8 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T8 == '1' then AArch32_TakeHypTrapException(0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HCR_EL2().TTLB == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HCR().TTLB == '1' then AArch32_TakeHypTrapException(0x03); else AArch32_DTLBI_VA(SecurityStateAtEL(EL1), Regime_EL10, VMID(), Broadcast_NSH, TLBILevel_Any, TLBI_AllAttr, R(t)); end; elsif PSTATE.EL == EL2 then AArch32_DTLBI_VA(SecurityStateAtEL(EL1), Regime_EL10, VMID(), Broadcast_NSH, TLBILevel_Any, TLBI_AllAttr, R(t)); elsif PSTATE.EL == EL3 then AArch32_DTLBI_VA(SecurityStateAtEL(EL3), Regime_EL30, VMID_NONE, Broadcast_NSH, TLBILevel_Any, TLBI_AllAttr, R(t)); end; 2026-03-26 20:27:25 2026-03_rel