<?xml version='1.0' encoding='utf-8'?>
<!DOCTYPE register_page SYSTEM "registers.dtd">
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<?xml-stylesheet href="one_register.xsl" type="text/xsl" ?>







<register_page>
  <registers>
  
    <register execution_state="AArch32" is_register="True" is_internal="True" is_stub_entry="False">
      <reg_short_name>ELR_hyp</reg_short_name>
        
        <reg_long_name>Exception Link Register (Hyp mode)</reg_long_name>



      
            <reg_condition otherwise="UNDEFINED">when FEAT_AA32 is implemented</reg_condition>
      




          <reg_reset_value>


          <reg_reset_special_text>
              <para>On a reset into an Exception level that is using AArch32 ELR_hyp is <arm-defined-word>UNKNOWN</arm-defined-word>.</para>
          </reg_reset_special_text>
      </reg_reset_value>

      <reg_mappings>
        



    
      
      <reg_mapping>
        
  

    

  

    <mapped_name filename="AArch64-elr_el2.xml">ELR_EL2</mapped_name>
  <mapped_type>Architectural</mapped_type>
      <mapped_execution_state>AArch64</mapped_execution_state>
    <mapped_from_startbit>31</mapped_from_startbit>
    <mapped_from_endbit>0</mapped_from_endbit>
    <mapped_to_startbit>31</mapped_to_startbit>
    <mapped_to_endbit>0</mapped_to_endbit>
    <mapped_from_rangeset output="31:0">
      <range>
        <msb>31</msb>
        <lsb>0</lsb>
      </range>
    </mapped_from_rangeset>
    <mapped_to_rangeset output="31:0">
      <range>
        <msb>31</msb>
        <lsb>0</lsb>
      </range>
    </mapped_to_rangeset>

      </reg_mapping>

      </reg_mappings>

        <reg_purpose>
          
    
      <purpose_text>
        <para>When taking an exception to Hyp mode, holds the address to return to.</para>
      </purpose_text>

        </reg_purpose>

      <reg_groups>
          <reg_group>Special</reg_group>
      </reg_groups>
      
      
        
      <reg_attributes>
          
    
      <attributes_text>
        <para>ELR_hyp is a 32-bit register.</para>
      </attributes_text>

      </reg_attributes>
      <reg_fieldsets>
        






<fields id="fieldset_0" length="32">
  <text_before_fields/>
  <field id="fieldset_0-31_0" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False">
    <field_name>ADDR</field_name>
    <field_shortdesc>Return address</field_shortdesc>
    <field_msb>31</field_msb>
    <field_lsb>0</field_lsb>
    <rel_range>31:0</rel_range>
    <field_description order="before">
      <para>Return address.</para>
    </field_description>
    <field_resets>
      <field_reset reset_type="Warm">
        <field_reset_standard_text>AU</field_reset_standard_text>
      </field_reset>
    </field_resets>
  </field>
  <text_after_fields/>
</fields>




<reg_fieldset length="32">
  <fieldat id="fieldset_0-31_0" msb="31" lsb="0"/>
</reg_fieldset>


      </reg_fieldsets>

      <access_mechanisms>
          


  
    
      <access_permission_text>
        <para>ELR_hyp is accessible only at Hyp mode and Monitor mode.</para>
      </access_permission_text>





    
        
        <access_mechanism accessor="MRSbanked ELR_hyp" type="SystemAccessor">
            <encoding>
            <access_instruction>MRS{&lt;c&gt;}{&lt;q&gt;} &lt;Rd&gt;, ELR_hyp</access_instruction>
                
                <enc n="R" v="0b0"/>
                
                <enc n="M" v="0b1"/>
                
                <enc n="M1" v="0b1110"/>
            </encoding>
        </access_mechanism>
    
        
        <access_mechanism accessor="MSRbanked ELR_hyp" type="SystemAccessor">
            <encoding>
            <access_instruction>MSR{&lt;c&gt;}{&lt;q&gt;} ELR_hyp, &lt;Rn&gt;</access_instruction>
                
                <enc n="R" v="0b0"/>
                
                <enc n="M" v="0b1"/>
                
                <enc n="M1" v="0b1110"/>
            </encoding>
        </access_mechanism>

      </access_mechanisms>

      <arch_variants>
      </arch_variants>
  </register>
</registers>
<timestamp>2026-03-26 20:27:25</timestamp>
<commit_id>2026-03_rel</commit_id>
</register_page>