FPSCR Floating-Point Status and Control Register when FEAT_AA32 is implemented FPSR Architectural AArch64 31 27 31 27 31 27 31 27 FPSR Architectural AArch64 7 7 7 7 7 7 7 7 FPSR Architectural AArch64 4 0 4 0 4 0 4 0 FPCR Architectural AArch64 26 15 26 15 26 15 26 15 FPCR Architectural AArch64 12 8 12 8 12 8 12 8 Provides floating-point system status information and control. Float It is IMPLEMENTATION DEFINED whether the Len and Stride fields can be programmed to nonzero values, which will cause some AArch32 floating-point instruction encodings to be UNDEFINED, or whether these fields are RAZ. Implemented only if the implementation includes the Advanced SIMD and floating-point functionality. FPSCR is a 32-bit register. N 31 31 31 Negative condition flag. This is updated by floating-point comparison operations. AU Z 30 30 30 Zero condition flag. This is updated by floating-point comparison operations. AU C 29 29 29 Carry condition flag. This is updated by floating-point comparison operations. AU V 28 28 28 Overflow condition flag. This is updated by floating-point comparison operations. AU QC 27 27 27 Cumulative saturation bit, Advanced SIMD only. This bit is set to 1 to indicate that an Advanced SIMD integer operation has saturated since 0 was last written to this bit. AU AHP 26 26 26 Alternative half-precision control bit: This bit is used only for conversions between half-precision floating-point and other floating-point formats. The data-processing instructions added as part of the FEAT_FP16 extension always use the IEEE half-precision format, and ignore the value of this bit. 0b0 IEEE half-precision format selected. 0b1 Alternative half-precision format selected. AU DN 25 25 25 Default NaN mode control bit: The value of this bit controls only scalar floating-point arithmetic. Advanced SIMD arithmetic always uses the Default NaN setting, regardless of the value of the DN bit. 0b0 NaN operands propagate through to the output of a floating-point operation. 0b1 Any operation involving one or more NaNs returns the Default NaN. AU FZ 24 24 24 Flush-to-zero mode control bit: The value of this bit controls only scalar floating-point arithmetic. Advanced SIMD arithmetic always uses the Flush-to-zero setting, regardless of the value of the FZ bit. This bit has no effect on half-precision calculations. 0b0 Flush-to-zero mode disabled. Behavior of the floating-point system is fully compliant with the IEEE 754 standard. 0b1 Flush-to-zero mode enabled. AU RMode 23 22 23:22 Rounding Mode control field. The encoding of this field is: The specified rounding mode is used by almost all scalar floating-point instructions. Advanced SIMD arithmetic always uses the Round to Nearest setting, regardless of the value of the RMode bits. 0b00 Round to Nearest (RN) mode. 0b01 Round towards Plus Infinity (RP) mode. 0b10 Round towards Minus Infinity (RM) mode. 0b11 Round towards Zero (RZ) mode. AU Stride 21 20 21:20 If this field is RW and is set to a value other than zero, some floating-point instruction encodings are UNDEFINED. The instruction pseudocode identifies these instructions. Arm strongly recommends that software never sets this field to a value other than zero. The value of this field is ignored when processing Advanced SIMD instructions. AU When an implementation implements FPSCR.{Stride,Len} as RAZ RAZ/WI FZ16 19 19 0 Flush-to-zero mode control bit on half-precision data-processing instructions: The value of this bit applies to both scalar and Advanced SIMD floating-point half-precision calculations. 0b0 Flush-to-zero mode disabled. Behavior of the floating-point system is fully compliant with the IEEE 754 standard. 0b1 Flush-to-zero mode enabled. AU When FEAT_FP16 is implemented 19 19 19 Reserved, RES0. Otherwise Len 18 16 18:16 If this field is RW and is set to a value other than zero, some floating-point instruction encodings are UNDEFINED. The instruction pseudocode identifies these instructions. Arm strongly recommends that software never sets this field to a value other than zero. The value of this field is ignored when processing Advanced SIMD instructions. AU When an implementation implements FPSCR.{Stride,Len} as RAZ RAZ/WI IDE 15 15 15 Input Denormal floating-point exception trap enable. When this bit is RW, it applies only to floating-point operations. Advanced SIMD operations always use untrapped floating-point exception handling in AArch32 state. 0b0 Untrapped exception handling selected. If the floating-point exception occurs, the IDC bit is set to 1. 0b1 Trapped exception handling selected. If the floating-point exception occurs, the PE does not update the IDC bit. AU When an implementation does not implement trapping of Input Denormal floating-point exceptions RAZ/WI 14 13 14:13 Reserved, RES0. IXE 12 12 12 Inexact floating-point exception trap enable. When this bit is RW, it applies only to floating-point operations. Advanced SIMD operations always use untrapped floating-point exception handling in AArch32 state. 0b0 Untrapped exception handling selected. If the floating-point exception occurs, the IXC bit is set to 1. 0b1 Trapped exception handling selected. If the floating-point exception occurs, the PE does not update the IXC bit. AU When an implementation does not implement trapping of Inexact floating-point exceptions RAZ/WI UFE 11 11 11 Underflow floating-point exception trap enable. When this bit is RW, it applies only to floating-point operations. Advanced SIMD operations always use untrapped floating-point exception handling in AArch32 state. 0b0 Untrapped exception handling selected. If the floating-point exception occurs, the UFC bit is set to 1. 0b1 Trapped exception handling selected. If the floating-point exception occurs and Flush-to-zero is not enabled, the PE does not update the UFC bit. AU When an implementation does not implement trapping of Underflow floating-point exceptions RAZ/WI OFE 10 10 10 Overflow floating-point exception trap enable. When this bit is RW, it applies only to floating-point operations. Advanced SIMD operations always use untrapped floating-point exception handling in AArch32 state. 0b0 Untrapped exception handling selected. If the floating-point exception occurs, the OFC bit is set to 1. 0b1 Trapped exception handling selected. If the floating-point exception occurs, the PE does not update the OFC bit. AU When an implementation does not implement trapping of Overflow floating-point exceptions RAZ/WI DZE 9 9 9 Divide by Zero floating-point exception trap enable. When this bit is RW, it applies only to floating-point operations. Advanced SIMD operations always use untrapped floating-point exception handling in AArch32 state. 0b0 Untrapped exception handling selected. If the floating-point exception occurs, the DZC bit is set to 1. 0b1 Trapped exception handling selected. If the floating-point exception occurs, the PE does not update the DZC bit. AU When an implementation does not implement trapping of Divide by Zero floating-point exceptions RAZ/WI IOE 8 8 8 Invalid Operation floating-point exception trap enable. When this bit is RW, it applies only to floating-point operations. Advanced SIMD operations always use untrapped floating-point exception handling in AArch32 state. 0b0 Untrapped exception handling selected. If the floating-point exception occurs, the IOC bit is set to 1. 0b1 Trapped exception handling selected. If the floating-point exception occurs, the PE does not update the IOC bit. AU When an implementation does not implement trapping of Invalid Operation floating-point exceptions RAZ/WI IDC 7 7 7 Input Denormal cumulative floating-point exception bit. This bit is set to 1 to indicate that the Input Denormal floating-point exception has occurred since 0 was last written to this bit. How VFP instructions update this bit depends on the value of the IDE bit. Advanced SIMD instructions set this bit if the Input Denormal floating-point exception occurs in one or more of the floating-point calculations performed by the instruction, regardless of the value of the IDE bit. AU 6 5 6:5 Reserved, RES0. IXC 4 4 4 Inexact cumulative floating-point exception bit. This bit is set to 1 to indicate that the Inexact floating-point exception has occurred since 0 was last written to this bit. How VFP instructions update this bit depends on the value of the IXE bit. Advanced SIMD instructions set this bit if the Inexact floating-point exception occurs in one or more of the floating-point calculations performed by the instruction, regardless of the value of the IXE bit. The criteria for the Inexact floating-point exception to occur are different in Flush-to-zero mode. For more information, see 'Flush-to-zero'. AU UFC 3 3 3 Underflow cumulative floating-point exception bit. This bit is set to 1 to indicate that the Underflow floating-point exception has occurred since 0 was last written to this bit. How VFP instructions update this bit depends on the value of the UFE bit. Advanced SIMD instructions set this bit if the Underflow floating-point exception occurs in one or more of the floating-point calculations performed by the instruction, if FPSCR.UFE is 0 or if Flush-to-zero is enabled. The criteria for the Underflow floating-point exception to occur are different in Flush-to-zero mode. For more information, see 'Flush-to-zero'. AU OFC 2 2 2 Overflow cumulative floating-point exception bit. This bit is set to 1 to indicate that the Overflow floating-point exception has occurred since 0 was last written to this bit. How VFP instructions update this bit depends on the value of the OFE bit. Advanced SIMD instructions set this bit if the Overflow floating-point exception occurs in one or more of the floating-point calculations performed by the instruction, regardless of the value of the OFE bit. AU DZC 1 1 1 Divide by Zero cumulative floating-point exception bit. This bit is set to 1 to indicate that the Divide by Zero floating-point exception has occurred since 0 was last written to this bit. How VFP instructions update this bit depends on the value of the DZE bit. Advanced SIMD instructions set this bit if the Divide by Zero floating-point exception occurs in one or more of the floating-point calculations performed by the instruction, regardless of the value of the DZE bit. AU IOC 0 0 0 Invalid Operation cumulative floating-point exception bit. This bit is set to 1 to indicate that the Invalid Operation floating-point exception has occurred since 0 was last written to this bit. How VFP instructions update this bit depends on the value of the IOE bit. Advanced SIMD instructions set this bit if the Invalid Operation floating-point exception occurs in one or more of the floating-point calculations performed by the instruction, regardless of the value of the IOE bit. AU VMRS{<c>}{<q>} <Rt>, <spec_reg> if !IsFeatureImplemented(FEAT_AA32) then Undefined(); elsif PSTATE.EL == EL0 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && CPTR_EL3().TFP == '1' then Undefined(); elsif IsFeatureImplemented(FEAT_AA64EL1) && !ELUsingAArch32(EL1) && !ELIsInHost(EL0) && CPACR_EL1().FPEN != '11' then if EL2Enabled() && (IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2)) && HCR_EL2().TGE == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x00); else AArch64_AArch32SystemAccessTrap(EL1, 0x07); end; elsif IsFeatureImplemented(FEAT_AA32EL1) && ELUsingAArch32(EL1) && ((IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) && SCR().NS == '1' && NSACR().cp10 == '0') || CPACR().cp10 IN {'0x'}) then Undefined(); elsif IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && ELIsInHost(EL0) && CPTR_EL2().FPEN != '11' then AArch64_AArch32SystemAccessTrap(EL2, 0x07); elsif IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && ELIsInHost(EL2) && CPTR_EL2().FPEN IN {'x0'} then AArch64_AArch32SystemAccessTrap(EL2, 0x07); elsif EL2Enabled() && (IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2)) && !ELIsInHost(EL2) && CPTR_EL2().TFP == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x07); elsif EL2Enabled() && (IsFeatureImplemented(FEAT_AA32EL1) && ELUsingAArch32(EL1)) && ((IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) && SCR().NS == '1' && NSACR().cp10 == '0') || HCPTR().TCP10 == '1') then AArch32_TakeHypTrapException(0x08); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && CPTR_EL3().TFP == '1' then if EL3SDDUndef() then Undefined(); else AArch64_AArch32SystemAccessTrap(EL3, 0x07); end; else R(t) = FPSCR(); end; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && CPTR_EL3().TFP == '1' then Undefined(); elsif (IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) && SCR().NS == '1' && NSACR().cp10 == '0') || CPACR().cp10 == '00' then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && !ELIsInHost(EL2) && CPTR_EL2().TFP == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x07); elsif ELIsInHost(EL2) && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && CPTR_EL2().FPEN IN {'x0'} then AArch64_AArch32SystemAccessTrap(EL2, 0x07); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && ((IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) && SCR().NS == '1' && NSACR().cp10 == '0') || HCPTR().TCP10 == '1') then AArch32_TakeHypTrapException(0x08); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && CPTR_EL3().TFP == '1' then if EL3SDDUndef() then Undefined(); else AArch64_AArch32SystemAccessTrap(EL3, 0x07); end; else R(t) = FPSCR(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && CPTR_EL3().TFP == '1' then Undefined(); elsif EL2Enabled() && ((IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) && SCR().NS == '1' && NSACR().cp10 == '0') || HCPTR().TCP10 == '1') then AArch32_TakeHypTrapException(0x00); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && CPTR_EL3().TFP == '1' then if EL3SDDUndef() then Undefined(); else AArch64_AArch32SystemAccessTrap(EL3, 0x07); end; else R(t) = FPSCR(); end; elsif PSTATE.EL == EL3 then if CPACR().cp10 == '00' then Undefined(); else R(t) = FPSCR(); end; end; VMSR{<c>}{<q>} <spec_reg>, <Rt> if !IsFeatureImplemented(FEAT_AA32) then Undefined(); elsif PSTATE.EL == EL0 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && CPTR_EL3().TFP == '1' then Undefined(); elsif IsFeatureImplemented(FEAT_AA64EL1) && !ELUsingAArch32(EL1) && !ELIsInHost(EL0) && CPACR_EL1().FPEN != '11' then if EL2Enabled() && (IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2)) && HCR_EL2().TGE == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x00); else AArch64_AArch32SystemAccessTrap(EL1, 0x07); end; elsif IsFeatureImplemented(FEAT_AA32EL1) && ELUsingAArch32(EL1) && ((IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) && SCR().NS == '1' && NSACR().cp10 == '0') || CPACR().cp10 IN {'0x'}) then Undefined(); elsif IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && ELIsInHost(EL0) && CPTR_EL2().FPEN != '11' then AArch64_AArch32SystemAccessTrap(EL2, 0x07); elsif IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && ELIsInHost(EL2) && CPTR_EL2().FPEN IN {'x0'} then AArch64_AArch32SystemAccessTrap(EL2, 0x07); elsif EL2Enabled() && (IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2)) && !ELIsInHost(EL2) && CPTR_EL2().TFP == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x07); elsif EL2Enabled() && (IsFeatureImplemented(FEAT_AA32EL1) && ELUsingAArch32(EL1)) && ((IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) && SCR().NS == '1' && NSACR().cp10 == '0') || HCPTR().TCP10 == '1') then AArch32_TakeHypTrapException(0x08); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && CPTR_EL3().TFP == '1' then if EL3SDDUndef() then Undefined(); else AArch64_AArch32SystemAccessTrap(EL3, 0x07); end; else FPSCR() = R(t); end; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && CPTR_EL3().TFP == '1' then Undefined(); elsif (IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) && SCR().NS == '1' && NSACR().cp10 == '0') || CPACR().cp10 == '00' then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && !ELIsInHost(EL2) && CPTR_EL2().TFP == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x07); elsif ELIsInHost(EL2) && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && CPTR_EL2().FPEN IN {'x0'} then AArch64_AArch32SystemAccessTrap(EL2, 0x07); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && ((IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) && SCR().NS == '1' && NSACR().cp10 == '0') || HCPTR().TCP10 == '1') then AArch32_TakeHypTrapException(0x08); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && CPTR_EL3().TFP == '1' then if EL3SDDUndef() then Undefined(); else AArch64_AArch32SystemAccessTrap(EL3, 0x07); end; else FPSCR() = R(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && CPTR_EL3().TFP == '1' then Undefined(); elsif EL2Enabled() && ((IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) && SCR().NS == '1' && NSACR().cp10 == '0') || HCPTR().TCP10 == '1') then AArch32_TakeHypTrapException(0x00); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && CPTR_EL3().TFP == '1' then if EL3SDDUndef() then Undefined(); else AArch64_AArch32SystemAccessTrap(EL3, 0x07); end; else FPSCR() = R(t); end; elsif PSTATE.EL == EL3 then if CPACR().cp10 == '00' then Undefined(); else FPSCR() = R(t); end; end; 2026-03-26 20:27:25 2026-03_rel