FPSID Floating-Point System ID register when FEAT_AA32EL1 is implemented Provides top-level information about the floating-point implementation. This register largely duplicates information held in the MIDR. Arm deprecates use of it. Float Implemented only if the implementation includes the Advanced SIMD and floating-point functionality. FPSID is a 32-bit register. Implementer 31 24 31:24 Implementer codes are the same as those used for the MIDR. For an implementation by Arm this field is 0x41, the ASCII code for A. This field has an IMPLEMENTATION DEFINED value. RO SW 23 23 23 Software bit. In Armv8, the only permitted value is 0. 0b0 The implementation provides a hardware implementation of the floating-point instructions. 0b1 The implementation supports only software emulation of the floating-point instructions. RO Subarchitecture 22 16 22:16 Subarchitecture version number. For a subarchitecture designed by Arm the most significant bit of this field, register bit[22], is 0. Values with a most significant bit of 0 that are not listed here are reserved. When the subarchitecture designer is not Arm, the most significant bit of this field, register bit[22], must be 1. Each implementer must maintain its own list of subarchitectures it has designed, starting at subarchitecture version number 0x40. In Armv8-A, the permitted values are 0b0000011 and 0b0000100. 0b0000000 VFPv1 architecture with an IMPLEMENTATION DEFINED subarchitecture. 0b0000001 VFPv2 architecture with Common VFP subarchitecture v1. 0b0000010 VFPv3 architecture, or later, with Common VFP subarchitecture v2. The VFP architecture version is indicated by the MVFR0 and MVFR1 registers. 0b0000011 VFPv3 architecture, or later, with Null subarchitecture. The entire floating-point implementation is in hardware, and no software support code is required. The VFP architecture version is indicated by the MVFR0 and MVFR1 registers. This value can be used only by an implementation that does not support the trap enable bits in the FPSCR. 0b0000100 VFPv3 architecture, or later, with Common VFP subarchitecture v3, and support for trap enable bits in FPSCR. The VFP architecture version is indicated by the MVFR0 and MVFR1 registers. RO PartNum 15 8 15:8 Part Number for the floating-point implementation, assigned by the implementer. This field has an IMPLEMENTATION DEFINED value. RO Variant 7 4 7:4 Variant number. Typically, this field distinguishes between different production variants of a single product. This field has an IMPLEMENTATION DEFINED value. RO Revision 3 0 3:0 Revision number for the floating-point implementation. This field has an IMPLEMENTATION DEFINED value. RO VMRS{<c>}{<q>} <Rt>, <spec_reg> if !IsFeatureImplemented(FEAT_AA32EL1) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && CPTR_EL3().TFP == '1' then Undefined(); elsif (IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) && SCR().NS == '1' && NSACR().cp10 == '0') || CPACR().cp10 == '00' then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && !ELIsInHost(EL2) && CPTR_EL2().TFP == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x07); elsif ELIsInHost(EL2) && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && CPTR_EL2().FPEN IN {'x0'} then AArch64_AArch32SystemAccessTrap(EL2, 0x07); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && ((IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) && SCR().NS == '1' && NSACR().cp10 == '0') || HCPTR().TCP10 == '1') then AArch32_TakeHypTrapException(0x08); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HCR_EL2().TID0 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x08); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HCR().TID0 == '1' then AArch32_TakeHypTrapException(0x08); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && CPTR_EL3().TFP == '1' then if EL3SDDUndef() then Undefined(); else AArch64_AArch32SystemAccessTrap(EL3, 0x07); end; else R(t) = FPSID(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && CPTR_EL3().TFP == '1' then Undefined(); elsif EL2Enabled() && ((IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) && SCR().NS == '1' && NSACR().cp10 == '0') || HCPTR().TCP10 == '1') then AArch32_TakeHypTrapException(0x00); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && CPTR_EL3().TFP == '1' then if EL3SDDUndef() then Undefined(); else AArch64_AArch32SystemAccessTrap(EL3, 0x07); end; else R(t) = FPSID(); end; elsif PSTATE.EL == EL3 then if CPACR().cp10 == '00' then Undefined(); else R(t) = FPSID(); end; end; VMSR{<c>}{<q>} <spec_reg>, <Rt> if !IsFeatureImplemented(FEAT_AA32EL1) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && CPTR_EL3().TFP == '1' then Undefined(); elsif (IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) && SCR().NS == '1' && NSACR().cp10 == '0') || CPACR().cp10 == '00' then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && !ELIsInHost(EL2) && CPTR_EL2().TFP == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x07); elsif ELIsInHost(EL2) && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && CPTR_EL2().FPEN IN {'x0'} then AArch64_AArch32SystemAccessTrap(EL2, 0x07); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && ((IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) && SCR().NS == '1' && NSACR().cp10 == '0') || HCPTR().TCP10 == '1') then AArch32_TakeHypTrapException(0x08); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HCR_EL2().TID0 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x08); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HCR().TID0 == '1' then AArch32_TakeHypTrapException(0x08); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && CPTR_EL3().TFP == '1' then if EL3SDDUndef() then Undefined(); else AArch64_AArch32SystemAccessTrap(EL3, 0x07); end; else return; end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && CPTR_EL3().TFP == '1' then Undefined(); elsif EL2Enabled() && ((IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) && SCR().NS == '1' && NSACR().cp10 == '0') || HCPTR().TCP10 == '1') then AArch32_TakeHypTrapException(0x00); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && CPTR_EL3().TFP == '1' then if EL3SDDUndef() then Undefined(); else AArch64_AArch32SystemAccessTrap(EL3, 0x07); end; else return; end; elsif PSTATE.EL == EL3 then if CPACR().cp10 == '00' then Undefined(); else return; end; end; 2026-03-26 20:27:25 2026-03_rel