HCPTR
Hyp Architectural Feature Trap Register
when FEAT_AA32EL2 is implemented
EL2
EL3
CPTR_EL2
Architectural
AArch64
31
0
31
0
31
0
31
0
Controls:
Trapping to Hyp mode of Non-secure access, at EL1 or EL0, to trace, and to Advanced SIMD and floating-point functionality.
Hyp mode access to trace, and to Advanced SIMD and floating-point functionality.
Accesses to this functionality:From Non-secure modes other than Hyp mode are also affected by settings in the CPACR and NSACR.From Hyp mode are also affected by settings in the NSACR.
Exceptions generated by the CPACR and NSACR controls are higher priority than those generated by the HCPTR controls.
Virt
If EL2 is not implemented, this register is RES0 from EL3.
HCPTR is a 32-bit register.
TCPAC
31
31
31
Traps Non-secure EL1 MRC and MCR accesses to the CPACR to Hyp mode, reported using EC syndrome value 0x03.
The CPACR is not accessible at EL0.
0b0
This control does not cause any instructions to be trapped.
0b1
Non-secure EL1 accesses to the CPACR are trapped to Hyp mode.
'0'
AU
TAM
30
30
0
Trap Activity Monitor access. Traps Non-secure EL1 and EL0 MRC, MCR, MRRC, and MCRR accesses to all Activity Monitors System registers to EL2, reported using EC syndrome values 0x03 and 0x04.
0b0
This control does not cause any instructions to be trapped.
0b1
Accesses from Non-secure EL1 and EL0 to Activity Monitors System registers are trapped to Hyp mode.
'0'
AU
When FEAT_AMUv1 is implemented
30
30
30
Reserved, RES0.
Otherwise
29
21
29:21
Reserved, RES0.
TTA
20
20
20
Traps Non-secure System register MRC, MCR, MRRC, and MCRR accesses to all implemented trace System registers to Hyp mode, reported using EC syndrome values 0x05 and 0x0C.
If the implementation does not include a trace unit, or does not include a System register interface to the trace unit registers, it is IMPLEMENTATION DEFINED whether this bit:
Is RES0.
Is RES1.
Can be written from Hyp mode, and from Secure Monitor mode when SCR.NS is 1.
If EL3 is implemented and is using AArch32, and the value of NSACR.NSTRCDIS is 1, in Non-secure state this field behaves as RAO/WI, regardless of its actual value.
FEAT_ETMv4 and FEAT_ETE do not permit EL0 to access the trace System registers. EL0 accesses to the trace System registers are UNDEFINED. A resulting Undefined Instruction exception is higher priority than an HCPTR.TTA Hyp Trap exception.The Arm architecture does not provide traps on trace register accesses through the optional memory-mapped debug interface.
System register accesses to the trace System registers can have side-effects. When a System register access is trapped, any side-effects that are normally associated with the access do not occur before the exception is taken.
0b0
This control does not cause any instructions to be trapped.
0b1
Any Non-secure System register access to an implemented trace System register is trapped to Hyp mode, unless the access is trapped to EL1 by a CPACR or NSACR control, or the access is from Non-secure EL0 and the definition of the register in the appropriate trace architecture specification indicates that the register is not accessible from EL0. A trapped instruction generates:
A Hyp Trap exception, if the exception is taken from Non-secure EL0 or EL1.
An Undefined Instruction exception taken to Hyp mode, if the exception is taken from Hyp mode.
'0'
AU
19
16
19:16
Reserved, RES0.
TASE
15
15
15
Traps Non-secure execution of Advanced SIMD instructions to Hyp mode, reported using EC syndrome value 0x07, when the value of HCPTR.TCP10 is 0.
When the value of HCPTR.TCP10 is 1, the value of this field is ignored.
If the implementation does not include Advanced SIMD and floating-point functionality, this field is RES1.
Otherwise, it is IMPLEMENTATION DEFINED whether this field is implemented as a RW field. If it is not implemented as a RW field, then it is RAZ/WI.
If EL3 is implemented and is using AArch32, and the value of NSACR.NSASEDIS is 1, in Non-secure state this field behaves as RAO/WI, regardless of its actual value. This applies even if the field is implemented as RAZ/WI.
For the list of instructions affected by this field, see 'Controls of Advanced SIMD operation that do not apply to floating-point operation'.
0b0
This control does not cause any instructions to be trapped.
0b1
When the value of HCPTR.TCP10 is 0, any attempt to execute an Advanced SIMD instruction in Non-secure state is trapped to Hyp mode, unless it is trapped to EL1 by a CPACR or NSACR control. A trapped instruction generates:
A Hyp Trap exception, if the exception is taken from Non-secure EL0 or EL1.
An Undefined Instruction exception taken to Hyp mode, if the exception is taken from Hyp mode.
'0'
AU
14
14
14
Reserved, RES0.
13
12
13:12
Reserved, RES1.
TCP11
11
11
0
The value of this field is ignored. If this field is programmed with a different value to the TCP10 bit then this field is UNKNOWN on a direct read of the HCPTR.
If the implementation does not include Advanced SIMD and floating-point functionality, this field is RES1.
If EL3 is implemented and is using AArch32, and the value of NSACR.cp10 is 0, in Non-secure state this field behaves as RAO/WI, regardless of its actual value.
'0'
AU
EL3 is implemented
EL3 is using AArch32
!IsCurrentSecurityState(SS_Secure)
NSACR.cp10 == '0'
RAO/WI
When FEAT_FP is implemented and FEAT_AdvSIMD is implemented
11
11
11
Reserved, RES1.
Otherwise
TCP10
10
10
0
Trap Non-secure accesses to Advanced SIMD and floating-point functionality to Hyp mode, reported using EC syndrome value 0x07:
The Advanced SIMD and floating-point features controlled by these fields are:
Execution of any floating-point or Advanced SIMD instruction.
Any access to the Advanced SIMD and floating-point registers D0-D31 and their views as S0-S31 and Q0-Q15.
Any access to the FPSCR, FPSID, MVFR0, MVFR1, MVFR2, or FPEXC System registers.
If the implementation does not include Advanced SIMD and floating-point functionality, this field is RES1.
If EL3 is implemented and is using AArch32, and the value of NSACR.cp10 is 0, in Non-secure state this field behaves as RAO/WI, regardless of its actual value.
0b0
This control does not cause any instructions to be trapped.
0b1
Any attempted access to Advanced SIMD and floating-point functionality from Non-secure state is trapped to Hyp mode, unless it is trapped to EL1 by a CPACR or NSACR control. A trapped instruction generates:
A Hyp Trap exception, if the exception is taken from Non-secure EL0 or EL1.
An Undefined Instruction exception taken to Hyp mode, if the exception is taken from Hyp mode.
'0'
AU
EL3 is implemented
EL3 is using AArch32
!IsCurrentSecurityState(SS_Secure)
NSACR.cp10 == '0'
RAO/WI
When FEAT_FP is implemented and FEAT_AdvSIMD is implemented
10
10
10
Reserved, RES1.
Otherwise
9
0
9:0
Reserved, RES1.
MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
if !IsFeatureImplemented(FEAT_AA32EL2) then
Undefined();
elsif PSTATE.EL == EL0 then
Undefined();
elsif PSTATE.EL == EL1 then
if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T1 == '1' then
AArch64_AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T1 == '1' then
AArch32_TakeHypTrapException(0x03);
else
Undefined();
end;
elsif PSTATE.EL == EL2 then
if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && CPTR_EL3().TCPAC == '1' then
Undefined();
elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && CPTR_EL3().TCPAC == '1' then
if EL3SDDUndef() then
Undefined();
else
AArch64_AArch32SystemAccessTrap(EL3, 0x03);
end;
else
R(t) = HCPTR();
end;
elsif PSTATE.EL == EL3 then
if SCR().NS == '0' then
Undefined();
else
R(t) = HCPTR();
end;
end;
MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
if !IsFeatureImplemented(FEAT_AA32EL2) then
Undefined();
elsif PSTATE.EL == EL0 then
Undefined();
elsif PSTATE.EL == EL1 then
if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T1 == '1' then
AArch64_AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T1 == '1' then
AArch32_TakeHypTrapException(0x03);
else
Undefined();
end;
elsif PSTATE.EL == EL2 then
if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && CPTR_EL3().TCPAC == '1' then
Undefined();
elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && CPTR_EL3().TCPAC == '1' then
if EL3SDDUndef() then
Undefined();
else
AArch64_AArch32SystemAccessTrap(EL3, 0x03);
end;
else
HCPTR() = R(t);
end;
elsif PSTATE.EL == EL3 then
if SCR().NS == '0' then
Undefined();
else
HCPTR() = R(t);
end;
end;
2026-03-26 20:27:25
2026-03_rel