HCR2 Hyp Configuration Register 2 when FEAT_AA32EL2 is implemented HCR_EL2 Architectural AArch64 31 0 63 32 31 0 63 32 Provides additional configuration controls for virtualization. Virt If EL2 is not implemented, this register is RES0 from EL3. HCR2 is a 32-bit register. 31 23 31:23 Reserved, RES0. TTLBIS 22 22 0 Trap TLB maintenance instructions that operate on the Inner Shareable domain. Traps execution of the following TLB maintenance instructions at EL1 to EL2: TLBIALLIS, TLBIASIDIS, TLBIMVAAIS, TLBIMVAALIS, TLBIMVAIS, and TLBIMVALIS When the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}, the Effective value of this field is 0. 0b0 This control does not cause any instructions to be trapped. 0b1 Non-secure EL1 execution of the specified TLB maintenance instructions is trapped to EL2. '0' AU When FEAT_EVT is implemented 22 22 22 Reserved, RES0. Otherwise 21 21 21 Reserved, RES0. TOCU 20 20 0 Trap cache maintenance instructions that operate to the Point of Unification. Traps execution of DCCMVAU, ICIALLU, and ICIMVAU at EL1 to EL2. If the Point of Unification is before any level of data cache, it is IMPLEMENTATION DEFINED whether the execution of any data or unified cache clean by VA to the Point of Unification instruction can be trapped when the value of this control is 1. If the Point of Unification is before any level of instruction cache, it is IMPLEMENTATION DEFINED whether the execution of any instruction cache invalidate to the Point of Unification instruction can be trapped when the value of this control is 1. When the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}, the Effective value of this field is 0. 0b0 This control does not cause any instructions to be trapped. 0b1 Non-secure execution of the specified cache maintenance instructions is trapped to EL2. '0' AU When FEAT_EVT is implemented 20 20 20 Reserved, RES0. Otherwise 19 19 19 Reserved, RES0. TICAB 18 18 0 Trap ICIALLUIS cache maintenance instructions. Traps execution of those cache maintenance instructions at EL1 to EL2. This applies to the following instructions: ICIALLUIS. If the Point of Unification is before any level of instruction cache, it is IMPLEMENTATION DEFINED whether the execution of any instruction cache invalidate to the Point of Unification instruction can be trapped when the value of this control is 1. When the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}, the Effective value of this field is 0. 0b0 This control does not cause any instructions to be trapped. 0b1 Non-secure EL1 execution of the specified cache maintenance instructions is trapped to EL2. '0' AU When FEAT_EVT is implemented 18 18 18 Reserved, RES0. Otherwise TID4 17 17 0 Trap ID group 4. Traps the following register accesses to EL2: EL1 reads of CCSIDR, CCSIDR2, CLIDR, and CSSELR. EL1 writes to CSSELR. When the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}, the Effective value of this field is 0. 0b0 This control does not cause any instructions to be trapped. 0b1 The specified Non-secure EL1 and EL0 accesses to ID group 4 registers are trapped to EL2. '0' AU When FEAT_EVT is implemented 17 17 17 Reserved, RES0. Otherwise 16 6 16:6 Reserved, RES0. TEA 5 5 0 Route synchronous External abort exceptions from EL0 and EL1 to EL2. 0b0 Does not route synchronous External abort exceptions from Non-secure EL0 and EL1 to EL2. 0b1 Route synchronous External abort exceptions from Non-secure EL0 and EL1 to EL2, if not routed to EL3. '0' AU When FEAT_RAS is implemented 5 5 5 Reserved, RES0. Otherwise TERR 4 4 0 Trap Error record accesses from EL1 to EL2. Traps MRC or MCR accesses, reported using EC syndrome value 0x03, and MRRC or MCRR accesses, reported using EC syndrome value 0x04, to the following registers from EL1 to EL2: ERRIDR, ERRSELR, ERXADDR, ERXADDR2, ERXCTLR, ERXCTLR2, ERXFR, ERXFR2, ERXMISC0, ERXMISC1, ERXMISC2, ERXMISC3, and ERXSTATUS. When FEAT_RASv1p1 is implemented, ERXMISC4, ERXMISC5, ERXMISC6, and ERXMISC7. 0b0 This control does not cause any instructions to be trapped. 0b1 Accesses to the specified registers from EL1 generate a Trap exception to EL2. '0' AU When FEAT_RAS is implemented 4 4 4 Reserved, RES0. Otherwise 3 2 3:2 Reserved, RES0. ID 1 1 1 Stage 2 Instruction access cacheability disable. For the Non-secure PL1&0 translation regime, when HCR.VM==1, this control forces all stage 2 translations for instruction accesses to Normal memory to be Non-cacheable. This bit has no effect on the EL2 translation regime. 0b0 This control has no effect on stage 2 of the Non-secure PL1&0 translation regime. 0b1 For the Non-secure PL1&0 translation regime, forces all stage 2 translations for instruction accesses to Normal memory to be Non-cacheable. '0' AU CD 0 0 0 Stage 2 Data access cacheability disable. When HCR.VM==1, this forces all stage 2 translations for data accesses and translation table walks to Normal memory to be Non-cacheable for the Non-secure PL1&0 translation regime. This bit has no effect on the EL2 translation regime. 0b0 This control has no effect on stage 2 of the Non-secure PL1&0 translation regime for data accesses and translation table walks. 0b1 For the Non-secure PL1&0 translation regime, forces all stage 2 translations for data accesses and translation table walks to Normal memory to be Non-cacheable. '0' AU MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>} if !IsFeatureImplemented(FEAT_AA32EL2) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T1 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T1 == '1' then AArch32_TakeHypTrapException(0x03); else Undefined(); end; elsif PSTATE.EL == EL2 then R(t) = HCR2(); elsif PSTATE.EL == EL3 then if SCR().NS == '0' then Undefined(); else R(t) = HCR2(); end; end; MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>} if !IsFeatureImplemented(FEAT_AA32EL2) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T1 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T1 == '1' then AArch32_TakeHypTrapException(0x03); else Undefined(); end; elsif PSTATE.EL == EL2 then HCR2() = R(t); elsif PSTATE.EL == EL3 then if SCR().NS == '0' then Undefined(); else HCR2() = R(t); end; end; 2026-03-26 20:27:25 2026-03_rel