HDCR
Hyp Debug Control Register
when FEAT_AA32EL2 is implemented
MDCR_EL2
Architectural
AArch64
31
0
31
0
31
0
31
0
Controls the trapping to Hyp mode of Non-secure accesses, at EL1 or lower, to functions provided by the debug and trace architectures and the Performance Monitors Extension.
Virt
If EL2 is not implemented, this register is RES0 from EL3, and other than for a direct read of the register, the PE behaves as if HDCR.HPMN == PMCR.N.
HDCR is a 32-bit register.
31
30
31:30
Reserved, RES0.
HPMFZO
29
29
0
Hyp Performance Monitors Freeze-on-overflow. Stop event counters on overflow.
If HDCR.HPMN is less than PMCR.N, this field affects the operation of event counters in the range [HDCR.HPMN .. (PMCR.N-1)].
This field does not affect the operation of other event counters and PMCCNTR.
The operation of this field applies even when EL2 is disabled in the current Security state.
0b0
Do not freeze on overflow.
0b1
Event counters do not count when PMOVSR[(PMCR.N-1):HDCR.HPMN] is nonzero.
AU
When FEAT_PMUv3p7 is implemented
29
29
29
Reserved, RES0.
Otherwise
MTPME
28
28
0
Multi-threaded PMU Enable. Enables use of the PMEVTYPER<n>.MT bits.
If FEAT_MTPMU is disabled for any other PE in the system that has the same level 1 Affinity as the PE, it is IMPLEMENTATION DEFINED whether the PE behaves as if this bit is 0.
0b0
FEAT_MTPMU is disabled. The Effective value of PMEVTYPER<n>.MT is zero.
0b1
PMEVTYPER<n>.MT bits not affected by this bit.
'1'
AU
When FEAT_MTPMU is implemented and EL3 is not implemented
28
28
28
Reserved, RES0.
Otherwise
TDCC
27
27
0
Trap DCC. Traps use of the Debug Comms Channel at EL1 and EL0 to EL2.
The DCC System registers trapped by this control are:
DBGDTRRXext, DBGDTRTXext, DBGDSCRint, DBGDCCINT, and, when the PE is in Non-debug state, DBGDTRRXint and DBGDTRTXint.
The traps are reported with EC syndrome value:
0x05 for trapped MRC and MCR accesses with coproc == 0b1110.
0x06 for trapped LDC to DBGDTRTXint and STC from DBGDTRRXint.
When the PE is in Debug state, HDCR.TDCC does not trap any accesses to:
DBGDTRRXint and DBGDTRTXint.
0b0
This control does not cause any register accesses to be trapped.
0b1
If EL2 is implemented and enabled in the current Security state, accesses to the DCC System registers at EL1 and EL0 generate a Hyp Trap exception, unless the access also generates a higher priority exception.
Traps on the DCC data transfer registers are ignored when the PE is in Debug state.
'0'
AU
When FEAT_FGT is implemented
27
27
27
Reserved, RES0.
Otherwise
HLP
26
26
0
Hypervisor Long event counter enable. Determines when unsigned overflow is recorded by an event counter overflow bit.
If the highest implemented Exception level is using AArch32, it is IMPLEMENTATION DEFINED whether this bit is read/write or RAZ/WI.
If HDCR.HPMN is less than PMCR.N, this bit affects the operation of event counters in the range [HDCR.HPMN..(PMCR.N-1)].
This field does not affect the operation of other event counters.
The operation of this field applies even when EL2 is disabled in the current Security state.
PMEVCNTR<n>[63:32] cannot be accessed directly in AArch32 state.
0b0
Event counter overflow on increment that causes unsigned overflow of PMEVCNTR<n>[31:0].
0b1
Event counter overflow on increment that causes unsigned overflow of PMEVCNTR<n>[63:0].
AU
When FEAT_PMUv3p5 is implemented
26
26
26
Reserved, RES0.
Otherwise
25
24
25:24
Reserved, RES0.
HCCD
23
23
0
Hypervisor Cycle Counter Disable. Prohibits PMCCNTR from counting at EL2.
This field does not affect the CPU_CYCLES event or any other event that counts cycles.
0b0
Cycle counting by PMCCNTR is not affected by this mechanism.
0b1
Cycle counting by PMCCNTR is prohibited at EL2.
'0'
AU
When FEAT_PMUv3p5 is implemented
23
23
23
Reserved, RES0.
Otherwise
22
20
22:20
Reserved, RES0.
TTRF
19
19
0
Traps use of the Trace Filter Control registers at EL1 to EL2 for MRC or MCR accesses, reported using EC syndrome value 0x03.
0b0
Accesses to TRFCR at EL1 are not affected by this control bit.
0b1
Accesses to TRFCR at EL1 generate a Hyp Trap exception.
'0'
AU
When FEAT_TRF is implemented
19
19
19
Reserved, RES0.
Otherwise
18
18
18
Reserved, RES0.
HPMD
17
17
0
Guest Performance Monitors Disable. Controls PMU operation in Hyp mode.
The counters affected by this field are:
Event counters PMEVCNTR<n> for values of n less than HDCR.HPMN.
If PMCR.DP is 1, the cycle counter PMCCNTR.
Other event counters are not affected by this field.
When PMCR.DP is 0, PMCCNTR is not affected by this field.
0b0
Counters are not affected by this mechanism.
0b1
Affected counters are prohibited from counting in Hyp mode.
If PMCR.DP is 1, then PMCCNTR is disabled in Hyp mode. Otherwise, PMCCNTR is not affected by this mechanism.
'0'
AU
When FEAT_PMUv3p1 is implemented and FEAT_Debugv8p2 is implemented
HPMD
17
17
0
Guest Performance Monitors Disable. Controls PMU operation in Hyp mode when ExternalSecureNoninvasiveDebugEnabled() is FALSE.
If ExternalSecureNoninvasiveDebugEnabled() is TRUE, then the event counters and PMCCNTR are not affected by this field.
Otherwise, the counters affected by this field are:
Event counters PMEVCNTR<n> for values of n less than HDCR.HPMN.
If PMCR.DP is 1, the cycle counter, PMCCNTR.
Other event counters are not affected by this field. When PMCR.DP is 0, PMCCNTR is not affected by this field.
0b0
Counters are not affected by this mechanism.
0b1
If ExternalSecureNoninvasiveDebugEnabled() is FALSE, then all the following apply:
Affected event counters are prohibited from counting in Hyp mode.
If PMCR.DP is 1, then PMCCNTR is disabled in Hyp mode. Otherwise, PMCCNTR is not affected by this mechanism.
'0'
AU
When FEAT_PMUv3p1 is implemented
17
17
17
Reserved, RES0.
Otherwise
16
12
16:12
Reserved, RES0.
TDRA
11
11
11
Trap Debug ROM Address register access. Traps Non-secure EL0 and EL1 System register MRC or MCR accesses, reported using EC syndrome value 0x05, and MRRC accesses, reported using EC syndrome value 0x0C, to the Debug ROM registers to Hyp mode.
If HCR.TGE or HDCR.TDE is 1, behavior is as if this bit is 1 other than for the purpose of a direct read.
0b0
This control does not cause any instructions to be trapped.
0b1
Non-secure EL0 and EL1 System register accesses to the DBGDRAR or DBGDSAR are trapped to Hyp mode, unless it is trapped by DBGDSCRext.UDCCdis.
'0'
AU
TDOSA
10
10
0
Trap debug OS-related register access. Traps Non-secure EL1 System register MRC or MCR accesses, reported using EC syndrome value 0x05, to the powerdown debug System registers to Hyp mode.
The registers for which accesses are trapped are as follows:
DBGOSLSR, DBGOSLAR, DBGOSDLR, and DBGPRCR.
Any IMPLEMENTATION DEFINED register with similar functionality that the implementation specifies as trapped by this bit.
These registers are not accessible at EL0.If HCR.TGE or HDCR.TDE is 1, behavior is as if this bit is 1 other than for the purpose of a direct read.
0b0
This control does not cause any instructions to be trapped.
0b1
Non-secure EL1 System register accesses to the powerdown debug System registers are trapped to Hyp mode.
'0'
AU
When FEAT_DoubleLock is implemented
TDOSA
10
10
0
Trap debug OS-related register access. Traps Non-secure EL1 System register MRC or MCR accesses, reported using EC syndrome value 0x05, to the powerdown debug System registers to Hyp mode.
The registers for which accesses are trapped are as follows:
DBGOSLSR, DBGOSLAR, and DBGPRCR.
Any IMPLEMENTATION DEFINED register with similar functionality that the implementation specifies as trapped by this bit.
It is IMPLEMENTATION DEFINED whether accesses to DBGOSDLR are trapped.
These registers are not accessible at EL0.If HCR.TGE or HDCR.TDE is 1, behavior is as if this bit is 1 other than for the purpose of a direct read.
0b0
This control does not cause any instructions to be trapped.
0b1
Non-secure EL1 System register accesses to the powerdown debug System registers are trapped to Hyp mode.
'0'
AU
Otherwise
TDA
9
9
9
Trap debug access. Traps Non-secure EL0 and EL1 System register MRC or MCR accesses, reported using EC syndrome value 0x05, to those debug System registers in the (coproc==0b1110) encoding space that are not trapped by either of the following:
HDCR.TDRA.
HDCR.TDOSA.
Traps of AArch32 accesses to DBGDTRRXint and DBGDTRTXint are ignored in Debug state.
If HCR.TGE or HDCR.TDE is 1, behavior is as if this bit is 1 other than for the purpose of a direct read.
0b0
This control does not cause any instructions to be trapped.
0b1
Non-secure EL0 or EL1 System register accesses to the debug System registers, other than the registers trapped by HDCR.TDRA and HDCR.TDOSA, are trapped to Hyp mode, unless it is trapped by DBGDSCRext.UDCCdis.
'0'
AU
TDE
8
8
8
Trap Debug exceptions. Controls routing of Debug exceptions, and defines the debug target Exception level, ELD.
For more information, see 'Routing debug exceptions'.
When HCR.TGE == 1, the PE behaves as if the value of this field is 1 for all purposes other than returning the value of a direct read of the register.
0b0
The debug target Exception level is EL1.
0b1
If EL2 is enabled for the current Effective value of SCR.NS, the debug target Exception level is EL2, otherwise the debug target Exception level is EL1.
The HDCR.{TDRA, TDOSA, TDA} fields are treated as being 1 for all purposes other than returning the result of a direct read of the register.
'0'
AU
HPME
7
7
0
Hyp Enable.
The counters affected by this field are event counters PMEVCNTR<n> for values of n greater than or equal to HDCR.HPMN and less than PMCR.N. This applies even when EL2 is disabled in the current Security state.
Other event counters and PMCCNTR are not affected by this field.
If HDCR.HPMN is equal to PMCR.N, then this field has no effect.
0b0
Affected counters are disabled and do not count.
0b1
Affected counters are enabled by PMCNTENSET.
'0'
AU
When FEAT_PMUv3 is implemented
7
7
7
Reserved, RES0.
Otherwise
TPM
6
6
0
Trap accesses of PMU registers. Enables a trap to EL2 on accesses of PMU registers.
The instructions affected by this control are:
MRC and MCR accesses to PMCCFILTR, PMCCNTR, PMCNTENCLR, PMCNTENSET, PMCR, PMEVCNTR<n>, PMEVTYPER<n>, PMINTENCLR, PMINTENSET, PMOVSR, PMOVSSET, PMSELR, PMSWINC, PMUSERENR, PMXEVCNTR, and PMXEVTYPER.
MRC accesses to PMCEID0 and PMCEID1.
MRRC and MCRR accesses to PMCCNTR.
If FEAT_PMUv3p1 is implemented, MRC accesses to PMCEID2 and PMCEID3.
If FEAT_PMUv3p4 is implemented, MRC accesses to PMMIR.
Unless the instruction generates a higher priority exception, trapped instructions generate a Hyp Trap exception.
Trapped instructions are reported using EC syndrome value 0x03 for MRC and MCR accesses, and 0x04 for MRRC and MCRR accesses.
0b0
Accesses of the specified PMU registers are not trapped by this mechanism.
0b1
Accesses of the specified PMU registers at EL1 and EL0 are trapped to EL2, unless the instruction generates a higher priority exception.
'0'
AU
When FEAT_PMUv3 is implemented
6
6
6
Reserved, RES0.
Otherwise
TPMCR
5
5
0
Trap PMCR accesses. Traps Non-secure EL0 and EL1 MCR or MRC accesses to the PMCR to Hyp mode, reported using EC syndrome value 0x03.
EL2 does not provide traps on Performance Monitor register accesses through the optional memory-mapped external debug interface.
0b0
This control does not cause any instructions to be trapped.
0b1
Non-secure EL0 and EL1 accesses to the PMCR are trapped to Hyp mode, unless it is trapped by PMUSERENR.EN.
'0'
AU
When FEAT_PMUv3 is implemented
5
5
5
Reserved, RES0.
Otherwise
HPMN
4
0
4:0
Defines the number of event counters PMEVCNTR<n> that are accessible from EL1 and, if permitted, from EL0.
HDCR.HPMN divides the event counters into a first range and a second range.
If HDCR.HPMN is not 0 and is less than the number of PMU event counters implemented by the PE, NUM_PMU_COUNTERS, then event counters [0..(HDCR.HPMN-1)] are in the first range, and the remaining event counters [HDCR.HPMN..(NUM_PMU_COUNTERS-1)] are in the second range.
If FEAT_HPMN0 is implemented and HDCR.HPMN is 0, then all of the following apply:
No event counters are in the first range.
All event counters are in the second range.
If HDCR.HPMN is equal to NUM_PMU_COUNTERS, or EL2 is not implemented, then all of the following apply:
All event counters are in the first range.
No event counters are in the second range.
All of the following apply for an event counter PMEVCNTR<n> in the first range:
The counter is accessible from EL1, EL2, and EL3.
The counter is accessible from EL0 if permitted by PMUSERENR.
If FEAT_PMUv3p5 is implemented, then PMCR.LP determines whether the counter overflow flag PMOVSSET[n] is set on unsigned overflow of PMEVCNTR<n>[31:0] or PMEVCNTR<n>[63:0]. PMEVCNTR<n>[63:32] cannot be accessed directly in AArch32 state.
PMCR.E and PMCNTENSET[n] enable the operation of the event counter.
All of the following apply for an event counter PMEVCNTR<n> in the second range:
The counter is accessible from EL2 and EL3.
If EL2 is disabled in the current Security state, then the event counter is accessible from EL1, and from EL0 if permitted by PMUSERENR.
If FEAT_PMUv3p5 is implemented, HDCR.HLP determines whether the counter overflow flag PMOVSSET[n] is set on unsigned overflow of PMEVCNTR<n>[31:0] or PMEVCNTR<n>[63:0]. PMEVCNTR<n>[63:32] cannot be accessed directly in AArch32 state.
HDCR.HPME and PMCNTENSET[n] enable the operation of the event counter.
Values greater than NUM_PMU_COUNTERS are reserved. If FEAT_HPMN0 is not implemented, then the value 0 is reserved.
If this field is set to a reserved value, then the following CONSTRAINED UNPREDICTABLE behaviors apply:
The value returned by a direct read of HDCR.HPMN is UNKNOWN.
The number of event counters in each of the first and second ranges is UNKNOWN. That is, either:
The PE behaves as if HDCR.HPMN is set to an UNKNOWN nonzero value less than or equal to NUM_PMU_COUNTERS.
All counters are in the second range and none are in the first range.
NUM_PMU_COUNTERS
When FEAT_PMUv3 is implemented
4
0
4:0
Reserved, RES0.
Otherwise
MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
if !IsFeatureImplemented(FEAT_AA32EL2) then
Undefined();
elsif PSTATE.EL == EL0 then
Undefined();
elsif PSTATE.EL == EL1 then
if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T1 == '1' then
AArch64_AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T1 == '1' then
AArch32_TakeHypTrapException(0x03);
else
Undefined();
end;
elsif PSTATE.EL == EL2 then
if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3().TDA == '1' then
Undefined();
elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3().TDA == '1' then
if EL3SDDUndef() then
Undefined();
else
AArch64_AArch32SystemAccessTrap(EL3, 0x03);
end;
else
R(t) = HDCR();
end;
elsif PSTATE.EL == EL3 then
if SCR().NS == '0' then
Undefined();
else
R(t) = HDCR();
end;
end;
MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
if !IsFeatureImplemented(FEAT_AA32EL2) then
Undefined();
elsif PSTATE.EL == EL0 then
Undefined();
elsif PSTATE.EL == EL1 then
if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T1 == '1' then
AArch64_AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T1 == '1' then
AArch32_TakeHypTrapException(0x03);
else
Undefined();
end;
elsif PSTATE.EL == EL2 then
if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3().TDA == '1' then
Undefined();
elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3().TDA == '1' then
if EL3SDDUndef() then
Undefined();
else
AArch64_AArch32SystemAccessTrap(EL3, 0x03);
end;
else
HDCR() = R(t);
end;
elsif PSTATE.EL == EL3 then
if SCR().NS == '0' then
Undefined();
else
HDCR() = R(t);
end;
end;
2026-03-26 20:27:25
2026-03_rel