<?xml version='1.0' encoding='utf-8'?>
<!DOCTYPE register_page SYSTEM "registers.dtd">
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<register_page>
  <registers>
  
    <register execution_state="AArch32" is_register="True" is_internal="True" is_stub_entry="False">
      <reg_short_name>HRMR</reg_short_name>
        
        <reg_long_name>Hyp Reset Management Register</reg_long_name>



      
            <reg_condition otherwise="UNDEFINED">when FEAT_AA32 is implemented</reg_condition>
      




          <reg_reset_value></reg_reset_value>

      <reg_mappings>
        



    
      
      <reg_mapping>
        
  

    

  

    <mapped_name filename="AArch64-rmr_el2.xml">RMR_EL2</mapped_name>
  <mapped_type>Architectural</mapped_type>
      <mapped_execution_state>AArch64</mapped_execution_state>
    <mapped_from_startbit>31</mapped_from_startbit>
    <mapped_from_endbit>0</mapped_from_endbit>
    <mapped_to_startbit>31</mapped_to_startbit>
    <mapped_to_endbit>0</mapped_to_endbit>
    <mapped_from_rangeset output="31:0">
      <range>
        <msb>31</msb>
        <lsb>0</lsb>
      </range>
    </mapped_from_rangeset>
    <mapped_to_rangeset output="31:0">
      <range>
        <msb>31</msb>
        <lsb>0</lsb>
      </range>
    </mapped_to_rangeset>

      </reg_mapping>

      </reg_mappings>

        <reg_purpose>
          
    
      <purpose_text>
        <para>If EL2 is the highest implemented Exception level and this register is implemented:</para>

      </purpose_text>
      <purpose_text>
        <list type="unordered">
<listitem><content>A write to the register at EL2 can request a Warm reset.</content>
</listitem><listitem><content>If EL2 can use AArch32 and AArch64, this register specifies the Execution state that the PE boots into on a Warm reset.</content>
</listitem></list>
      </purpose_text>

        </reg_purpose>

      <reg_groups>
            <reg_group>Virt</reg_group>
            <reg_group>Reset Management</reg_group>
      </reg_groups>
      <reg_configuration>
        
    
      <configuration_text>
        <para>Only implemented if EL2 is the highest implemented Exception level. In this case:</para>

      </configuration_text>
      <configuration_text>
        <list type="unordered">
<listitem><content>If EL2 can use AArch32 and AArch64 then this register must be implemented.</content>
</listitem><listitem><content>If EL2 cannot use AArch64 then it is <arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word> whether the register is implemented.</content>
</listitem></list>
      </configuration_text>

      </reg_configuration>
      
      
        
      <reg_attributes>
          
    
      <attributes_text>
        <para>HRMR is a 32-bit register.</para>
      </attributes_text>

      </reg_attributes>
      <reg_fieldsets>
        






<fields id="fieldset_0" length="32">
  <text_before_fields/>
  <field id="fieldset_0-31_2" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False" rwtype="RES0">
    <field_msb>31</field_msb>
    <field_lsb>2</field_lsb>
    <rel_range>31:2</rel_range>
    <field_description order="before"/>
    <field_description order="before">
      <para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para>
    </field_description>
  </field>
  <field id="fieldset_0-1_1" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False">
    <field_name>RR</field_name>
    <field_msb>1</field_msb>
    <field_lsb>1</field_lsb>
    <rel_range>1</rel_range>
    <field_description order="before">
      <para>Reset Request. Setting this bit to 1 requests a Warm reset.</para>
    </field_description>
    <field_resets>
      <field_reset reset_type="Warm">
        <field_reset_number>'0'</field_reset_number>
      </field_reset>
    </field_resets>
  </field>
  <field id="fieldset_0-0_0-1" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False" reserved_type="RAZ/WI">
    <field_name>AA64</field_name>
    <field_msb>0</field_msb>
    <field_lsb>0</field_lsb>
    <rel_range>0</rel_range>
    <field_description order="before">
      <para>Determines which Execution state the PE boots into after a Warm reset:</para>
    </field_description>
    <field_description order="after">
      <para>On coming out of the Warm reset, execution starts at the <arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word> reset vector address of the specified Execution state.</para>
    </field_description>
    <field_values impdef="False">
      <field_value_instance>
        <field_value>0b0</field_value>
        <field_value_description>
          <para>AArch32.</para>
        </field_value_description>
      </field_value_instance>
      <field_value_instance>
        <field_value>0b1</field_value>
        <field_value_description>
          <para>AArch64.</para>
        </field_value_description>
      </field_value_instance>
    </field_values>
    <field_resets>
      <field_reset reset_type="Cold">
        <field_reset_number>'0'</field_reset_number>
      </field_reset>
    </field_resets>
    <fields_condition>When Implementation can reset into AArch64 state</fields_condition>
  </field>
  <field id="fieldset_0-0_0-2" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False" rwtype="RAZ/WI">
    <field_msb>0</field_msb>
    <field_lsb>0</field_lsb>
    <rel_range>0</rel_range>
    <field_description order="before"/>
    <field_description order="before">
      <para>Reserved, RAZ/WI.</para>
    </field_description>
    <fields_condition>Otherwise</fields_condition>
  </field>
  <text_after_fields/>
</fields>




<reg_fieldset length="32">
  <fieldat id="fieldset_0-31_2" msb="31" lsb="2"/>
  <fieldat id="fieldset_0-1_1" msb="1" lsb="1"/>
  <fieldat id="fieldset_0-0_0-1" msb="0" lsb="0"/>
</reg_fieldset>


      </reg_fieldsets>

      <access_mechanisms>
          






    
        
        <access_mechanism accessor="MRC HRMR" type="SystemAccessor">
            <encoding>
            <access_instruction>MRC{&lt;c&gt;}{&lt;q&gt;} &lt;coproc&gt;, {#}&lt;opc1&gt;, &lt;Rt&gt;, &lt;CRn&gt;, &lt;CRm&gt;{, {#}&lt;opc2&gt;}</access_instruction>
                
                <enc n="coproc" v="0b1111"/>
                
                <enc n="opc1" v="0b100"/>
                
                <enc n="CRn" v="0b1100"/>
                
                <enc n="CRm" v="0b0000"/>
                
                <enc n="opc2" v="0b010"/>
            </encoding>
            <access_permission>
                <ps name="MRC" sections="1" secttype="access_permission">
                <pstext>
if !IsFeatureImplemented(FEAT_AA32) then
    Undefined();
elsif PSTATE.EL == EL1 &amp;&amp; EL2Enabled() &amp;&amp; IsHighestEL(EL2) &amp;&amp; IsFeatureImplemented(FEAT_AA64EL2) &amp;&amp; !ELUsingAArch32(EL2) &amp;&amp; HSTR_EL2().T12 == '1' then
    AArch64_AArch32SystemAccessTrap(EL2, 0x03);
elsif PSTATE.EL == EL1 &amp;&amp; EL2Enabled() &amp;&amp; IsHighestEL(EL2) &amp;&amp; IsFeatureImplemented(FEAT_AA32EL2) &amp;&amp; ELUsingAArch32(EL2) &amp;&amp; HSTR().T12 == '1' then
    AArch32_TakeHypTrapException(0x03);
elsif PSTATE.EL == EL2 &amp;&amp; IsHighestEL(EL2) then
    R(t) = HRMR();
else
    Undefined();
end;
                </pstext>
                </ps>
            </access_permission>
        </access_mechanism>
    
        
        <access_mechanism accessor="MCR HRMR" type="SystemAccessor">
            <encoding>
            <access_instruction>MCR{&lt;c&gt;}{&lt;q&gt;} &lt;coproc&gt;, {#}&lt;opc1&gt;, &lt;Rt&gt;, &lt;CRn&gt;, &lt;CRm&gt;{, {#}&lt;opc2&gt;}</access_instruction>
                
                <enc n="coproc" v="0b1111"/>
                
                <enc n="opc1" v="0b100"/>
                
                <enc n="CRn" v="0b1100"/>
                
                <enc n="CRm" v="0b0000"/>
                
                <enc n="opc2" v="0b010"/>
            </encoding>
            <access_permission>
                <ps name="MCR" sections="1" secttype="access_permission">
                <pstext>
if !IsFeatureImplemented(FEAT_AA32) then
    Undefined();
elsif PSTATE.EL == EL1 &amp;&amp; EL2Enabled() &amp;&amp; IsHighestEL(EL2) &amp;&amp; IsFeatureImplemented(FEAT_AA64EL2) &amp;&amp; !ELUsingAArch32(EL2) &amp;&amp; HSTR_EL2().T12 == '1' then
    AArch64_AArch32SystemAccessTrap(EL2, 0x03);
elsif PSTATE.EL == EL1 &amp;&amp; EL2Enabled() &amp;&amp; IsHighestEL(EL2) &amp;&amp; IsFeatureImplemented(FEAT_AA32EL2) &amp;&amp; ELUsingAArch32(EL2) &amp;&amp; HSTR().T12 == '1' then
    AArch32_TakeHypTrapException(0x03);
elsif PSTATE.EL == EL2 &amp;&amp; IsHighestEL(EL2) then
    HRMR() = R(t);
else
    Undefined();
end;
                </pstext>
                </ps>
            </access_permission>
        </access_mechanism>

      </access_mechanisms>

      <arch_variants>
      </arch_variants>
  </register>
</registers>
<timestamp>2026-03-26 20:27:25</timestamp>
<commit_id>2026-03_rel</commit_id>
</register_page>