HSCTLR Hyp System Control Register when FEAT_AA32EL2 is implemented SCTLR_EL2 Architectural AArch64 31 0 31 0 31 0 31 0 Provides top-level control of the system operation in Hyp mode. Virt If EL2 is not implemented, this register is RES0 from EL3. HSCTLR is a 32-bit register. DSSBS 31 31 0 Default PSTATE.SSBS value on Exception Entry. The defined values are: 0b0 PSTATE.SSBS is set to 0 on an exception to Hyp mode. 0b1 PSTATE.SSBS is set to 1 on an exception to Hyp mode. ID When FEAT_SSBS is implemented 31 31 31 Reserved, RES0. Otherwise TE 30 30 30 T32 Exception Enable. This bit controls whether exceptions to EL2 are taken to A32 or T32 state: 0b0 Exceptions, including reset, taken to A32 state. 0b1 Exceptions, including reset, taken to T32 state. ID 29 28 29:28 Reserved, RES1. 27 26 27:26 Reserved, RES0. EE 25 25 0 The value of the PSTATE.E bit on entry to Hyp mode, the endianness of stage 1 translation table walks in the EL2 translation regime, and the endianness of stage 2 translation table walks in the PL1&0 translation regime. 0b0 Little-endian. PSTATE.E is cleared to 0 on entry to Hyp mode. Stage 1 translation table walks in the EL2 translation regime, and stage 2 translation table walks in the PL1&0 translation regime are little-endian. 0b1 Big-endian. PSTATE.E is set to 1 on entry to Hyp mode. Stage 1 translation table walks in the EL2 translation regime, and stage 2 translation table walks in the PL1&0 translation regime are big-endian. ID When FEAT_MixedEnd is implemented 25 25 0 Explicit data accesses at EL1, and stage 1 translation table walks in the EL1&0 translation regime are big-endian. Reserved, RES1. When FEAT_BigEnd is implemented 25 25 0 Explicit data accesses at EL1, and stage 1 translation table walks in the EL1&0 translation regime are little-endian. Reserved, RES0. Otherwise 24 24 24 Reserved, RES0. 23 22 23:22 Reserved, RES1. 21 20 21:20 Reserved, RES0. WXN 19 19 19 Write permission implies XN (Execute-never). For the EL2 translation regime, this bit can force all memory regions that are writable to be treated as XN. This bit applies only when HSCTLR.M bit is set. This bit is permitted to be cached in a TLB. 0b0 This control has no effect on memory access permissions. 0b1 Any region that is writable in the EL2 translation regime is forced to XN for accesses from software executing at EL2. AU 18 18 18 Reserved, RES1. 17 17 17 Reserved, RES0. 16 16 16 Reserved, RES1. 15 13 15:13 Reserved, RES0. I 12 12 12 Instruction access Cacheability control, for accesses at EL2: This bit has no effect on the PL1&0 translation regime. 0b0 All instruction access to Normal memory from EL2 are Non-cacheable for all levels of instruction and unified cache. If the value of HSCTLR.M is 0, instruction accesses from stage 1 of the EL2 translation regime are to Normal, Outer Shareable, Inner Non-cacheable, Outer Non-cacheable memory. 0b1 All instruction access to Normal memory from EL2 can be cached at all levels of instruction and unified cache. If the value of HSCTLR.M is 0, instruction accesses from stage 1 of the EL2 translation regime are to Normal, Outer Shareable, Inner Write-Through, Outer Write-Through memory. '0' AU 11 11 11 Reserved, RES1. 10 9 10:9 Reserved, RES0. SED 8 8 8 SETEND instruction disable. Disables SETEND instructions at EL2. If the implementation does not support mixed-endian operation at EL2, this bit is RES1. 0b0 SETEND instruction execution is enabled at EL2. 0b1 SETEND instructions are UNDEFINED at EL2. AU ITD 7 7 7 IT Disable. Disables some uses of IT instructions at EL2. If an instruction in an active IT block that would be disabled by this field sets this field to 1, then behavior is CONSTRAINED UNPREDICTABLE. For more information, see 'Changes to an ITD control by an instruction in an IT block'. ITD is optional, but if it is implemented in the HSCTLR, then it must also be implemented in the SCTLR_EL1, SCTLR_EL2, and SCTLR. 0b0 All IT instruction functionality is enabled at EL2. 0b1 Any attempt at EL2 to execute any of the following is UNDEFINED: All encodings of the IT instruction with hw1[3:0]!=1000. All encodings of the subsequent instruction with the following values for hw1: 0b11xxxxxxxxxxxxxx: All 32-bit instructions, and the 16-bit instructions B, UDF, SVC, LDM, and STM. 0b1011xxxxxxxxxxxx: All instructions in 'Miscellaneous 16-bit instructions'. 0b10100xxxxxxxxxxx: ADD Rd, PC, #imm 0b01001xxxxxxxxxxx: LDR Rd, [PC, #imm] 0b0100x1xxx1111xxx: ADD Rdn, PC; CMP Rn, PC; MOV Rd, PC; BX PC; BLX PC. 0b010001xx1xxxx111: ADD PC, Rm; CMP PC, Rm; MOV PC, Rm. This pattern also covers unpredictable cases with BLX Rn. These instructions are always UNDEFINED, regardless of whether they would pass or fail the condition code check that applies to them as a result of being in an IT block. It is IMPLEMENTATION DEFINED whether the IT instruction is treated as: A 16-bit instruction, that can only be followed by another 16-bit instruction. The first half of a 32-bit instruction. This means that, for the situations that are UNDEFINED, either the second 16-bit instruction or the 32-bit instruction is UNDEFINED. An implementation might vary dynamically as to whether IT is treated as a 16-bit instruction or the first half of a 32-bit instruction. AU When an implementation does not implement ITD RAZ/WI 6 6 6 Reserved, RES0. CP15BEN 5 5 5 System instruction memory barrier enable. Enables accesses to the DMB, DSB, and ISB System instructions in the (coproc==0b1111) encoding space from EL2: CP15BEN is optional, but if it is implemented in the HSCTLR, then it must also be implemented in the SCTLR_EL1, SCTLR_EL2, and SCTLR. 0b0 EL2 execution of the CP15DMB, CP15DSB, and CP15ISB instructions is UNDEFINED. 0b1 EL2 execution of the CP15DMB, CP15DSB, and CP15ISB instructions is enabled. AU When an implementation does not implement CP15BEN RAO/WI LSMAOE 4 4 0 Load Multiple and Store Multiple Atomicity and Ordering Enable. This bit is permitted to be cached in a TLB. 0b0 For all memory accesses at EL2, T32 and A32 Load Multiple and Store Multiple can have an interrupt taken during the sequence memory accesses, and the memory accesses are not required to be ordered. 0b1 The ordering and interrupt behavior of T32 and A32 Load Multiple and Store Multiple at EL2 is as defined for Armv8.0. '1' AU When FEAT_LSMAOC is implemented 4 4 4 Reserved, RES1. Otherwise nTLSMD 3 3 0 No Trap Load Multiple and Store Multiple to Device-nGRE/Device-nGnRE/Device-nGnRnE memory. This bit is permitted to be cached in a TLB. 0b0 All memory accesses by T32 and A32 Load Multiple and Store Multiple at EL2 that are marked at stage 1 as Device-nGRE/Device-nGnRE/Device-nGnRnE memory are trapped and generate a stage 1 Alignment fault. 0b1 All memory accesses by T32 and A32 Load Multiple and Store Multiple at EL2 that are marked at stage 1 as Device-nGRE/Device-nGnRE/Device-nGnRnE memory are not trapped. '1' AU When FEAT_LSMAOC is implemented 3 3 3 Reserved, RES1. Otherwise C 2 2 2 Cacheability control, for data accesses at EL2: This bit has no effect on the PL1&0 translation regime. 0b0 All data access to Normal memory from EL2, and all accesses to the EL2 translation tables, are Non-cacheable for all levels of data and unified cache. 0b1 All data access to Normal memory from EL2, and all accesses to the EL2 translation tables, can be cached at all levels of data and unified cache. '0' AU A 1 1 1 Alignment check enable. This is the enable bit for Alignment fault checking at EL2: Load/store exclusive and load-acquire/store-release instructions have an alignment check regardless of the value of the A bit. 0b0 Alignment fault checking disabled when executing at EL2. Instructions that load or store one or more registers, other than load/store exclusive and load-acquire/store-release, do not check that the address being accessed is aligned to the size of the data element or data elements being accessed. 0b1 Alignment fault checking enabled when executing at EL2. All instructions that load or store one or more registers have an alignment check that the address being accessed is aligned to the size of the data element or data elements being accessed. If this check fails it causes an Alignment fault, which is taken as a Data Abort exception. AU M 0 0 0 MMU enable for EL2 stage 1 address translation. Possible values of this bit are: 0b0 EL2 stage 1 address translation disabled. See the HSCTLR.I field for the behavior of instruction accesses to Normal memory. 0b1 EL2 stage 1 address translation enabled. '0' AU MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>} if !IsFeatureImplemented(FEAT_AA32EL2) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T1 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T1 == '1' then AArch32_TakeHypTrapException(0x03); else Undefined(); end; elsif PSTATE.EL == EL2 then R(t) = HSCTLR(); elsif PSTATE.EL == EL3 then if SCR().NS == '0' then Undefined(); else R(t) = HSCTLR(); end; end; MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>} if !IsFeatureImplemented(FEAT_AA32EL2) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T1 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T1 == '1' then AArch32_TakeHypTrapException(0x03); else Undefined(); end; elsif PSTATE.EL == EL2 then HSCTLR() = R(t); elsif PSTATE.EL == EL3 then if SCR().NS == '0' then Undefined(); else HSCTLR() = R(t); end; end; 2026-03-26 20:27:25 2026-03_rel