HTCR
Hyp Translation Control Register
when FEAT_AA32EL2 is implemented
TCR_EL2
Architectural
AArch64
31
0
31
0
31
0
31
0
The control register for stage 1 of the EL2 translation regime.
This stage of translation always uses the Long-descriptor translation table format.
Memory
Virt
If EL2 is not implemented, this register is RES0 from EL3.
HTCR is a 32-bit register.
31
31
31
Reserved, RES1.
IMPLEMENTATION DEFINED
30
30
30
IMPLEMENTATION DEFINED.
AU
29
29
29
Reserved, RES0.
HWU62
28
28
0
Hardware Use. Indicates IMPLEMENTATION DEFINED hardware use of bit[62] of the stage 1 translation table Block or Page entry.
The Effective value of this field is 0 if the value of HTCR.HPD is 0.
0b0
Bit[62] of each stage 1 translation table Block or Page entry cannot be used by hardware for an IMPLEMENTATION DEFINED purpose.
0b1
Bit[62] of each stage 1 translation table Block or Page entry can be used by hardware for an IMPLEMENTATION DEFINED purpose if the value of HTCR.HPD is 1.
AU
When FEAT_HPDS2 is implemented
28
28
28
Reserved, RES0.
Otherwise
HWU61
27
27
0
Hardware Use. Indicates IMPLEMENTATION DEFINED hardware use of bit[61] of the stage 1 translation table Block or Page entry.
The Effective value of this field is 0 if the value of HTCR.HPD is 0.
0b0
Bit[61] of each stage 1 translation table Block or Page entry cannot be used by hardware for an IMPLEMENTATION DEFINED purpose.
0b1
Bit[61] of each stage 1 translation table Block or Page entry can be used by hardware for an IMPLEMENTATION DEFINED purpose if the value of HTCR.HPD is 1.
AU
When FEAT_HPDS2 is implemented
27
27
27
Reserved, RES0.
Otherwise
HWU60
26
26
0
Hardware Use. Indicates IMPLEMENTATION DEFINED hardware use of bit[60] of the stage 1 translation table Block or Page entry.
The Effective value of this field is 0 if the value of HTCR.HPD is 0.
0b0
Bit[60] of each stage 1 translation table Block or Page entry cannot be used by hardware for an IMPLEMENTATION DEFINED purpose.
0b1
Bit[60] of each stage 1 translation table Block or Page entry can be used by hardware for an IMPLEMENTATION DEFINED purpose if the value of HTCR.HPD is 1.
AU
When FEAT_HPDS2 is implemented
26
26
26
Reserved, RES0.
Otherwise
HWU59
25
25
0
Hardware Use. Indicates IMPLEMENTATION DEFINED hardware use of bit[59] of the stage 1 translation table Block or Page entry.
The Effective value of this field is 0 if the value of HTCR.HPD is 0.
0b0
Bit[59] of each stage 1 translation table Block or Page entry cannot be used by hardware for an IMPLEMENTATION DEFINED purpose.
0b1
Bit[59] of each stage 1 translation table Block or Page entry can be used by hardware for an IMPLEMENTATION DEFINED purpose if the value of HTCR.HPD is 1.
AU
When FEAT_HPDS2 is implemented
25
25
25
Reserved, RES0.
Otherwise
HPD
24
24
0
Hierarchical Permission Disables. This affects the hierarchical control bits, APTable, XNTable, and PXNTable, in the PL2 translation regime.
When disabled, the permissions are treated as if the bits are zero.
0b0
Hierarchical permissions are enabled.
0b1
Hierarchical permissions are disabled.
AU
When FEAT_AA32HPD is implemented
24
24
24
Reserved, RES0.
Otherwise
23
23
23
Reserved, RES1.
22
14
22:14
Reserved, RES0.
SH0
13
12
13:12
Shareability attribute for memory associated with translation table walks using HTTBR.
Other values are reserved. The effect of programming this field to a Reserved value is that behavior is CONSTRAINED UNPREDICTABLE.
0b00
Non-shareable.
0b10
Outer Shareable.
0b11
Inner Shareable.
AU
ORGN0
11
10
11:10
Outer cacheability attribute for memory associated with translation table walks using HTTBR.
0b00
Normal memory, Outer Non-cacheable.
0b01
Normal memory, Outer Write-Back Read-Allocate Write-Allocate Cacheable.
0b10
Normal memory, Outer Write-Through Read-Allocate No Write-Allocate Cacheable.
0b11
Normal memory, Outer Write-Back Read-Allocate No Write-Allocate Cacheable.
AU
IRGN0
9
8
9:8
Inner cacheability attribute for memory associated with translation table walks using HTTBR.
0b00
Normal memory, Inner Non-cacheable.
0b01
Normal memory, Inner Write-Back Read-Allocate Write-Allocate Cacheable.
0b10
Normal memory, Inner Write-Through Read-Allocate No Write-Allocate Cacheable.
0b11
Normal memory, Inner Write-Back Read-Allocate No Write-Allocate Cacheable.
AU
7
3
7:3
Reserved, RES0.
T0SZ
2
0
2:0
The size offset of the memory region addressed by HTTBR. The region size is 2(32-T0SZ) bytes.
AU
MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
if !IsFeatureImplemented(FEAT_AA32EL2) then
Undefined();
elsif PSTATE.EL == EL0 then
Undefined();
elsif PSTATE.EL == EL1 then
if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T2 == '1' then
AArch64_AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T2 == '1' then
AArch32_TakeHypTrapException(0x03);
else
Undefined();
end;
elsif PSTATE.EL == EL2 then
R(t) = HTCR();
elsif PSTATE.EL == EL3 then
if SCR().NS == '0' then
Undefined();
else
R(t) = HTCR();
end;
end;
MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
if !IsFeatureImplemented(FEAT_AA32EL2) then
Undefined();
elsif PSTATE.EL == EL0 then
Undefined();
elsif PSTATE.EL == EL1 then
if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T2 == '1' then
AArch64_AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T2 == '1' then
AArch32_TakeHypTrapException(0x03);
else
Undefined();
end;
elsif PSTATE.EL == EL2 then
HTCR() = R(t);
elsif PSTATE.EL == EL3 then
if SCR().NS == '0' then
Undefined();
else
HTCR() = R(t);
end;
end;
2026-03-26 20:27:25
2026-03_rel