HTTBR Hyp Translation Table Base Register when FEAT_AA32EL2 is implemented TTBR0_EL2 Architectural AArch64 47 0 47 0 47 0 47 0 Holds the base address of the translation table for the initial lookup for stage 1 of an address translation in the EL2 translation regime, and other information for this translation regime. Memory Virt If EL2 is not implemented, this register is RES0 from EL3. HTTBR is a 64-bit register. 63 48 63:48 Reserved, RES0. BADDR 47 1 47:1 Translation table base address, bits[47:x], Bits [x-1:1] are RES0, with the additional requirement that if bits[x-1:3] are not all zero, this is a misaligned translation table base address, with effects that are CONSTRAINED UNPREDICTABLE, and must be one of the following: Register bits [x-1:3] are treated as if all the bits are zero. The value read back from these bits is either the value written or zero. The result of the calculation of an address for a translation table walk using this register can be corrupted in those bits that are nonzero. x is determined from the value of HTCR.T0SZ as follows: If HTCR.T0SZ is 0 or 1, x = 5 - HTCR.T0SZ. If HTCR.T0SZ is greater than 1, x = 14 - HTCR.T0SZ. If bits[47:40] of the translation table base address are not zero, an Address size fault is generated. AU CnP 0 0 0 Common not Private. This bit indicates whether each entry that is pointed to by HTTBR is a member of a common set that can be used by every PE in the Inner Shareable domain for which the value of HTTBR.CnP is 1. If the value of the HTTBR.CnP bit is 1 on multiple PEs in the same Inner Shareable domain and those HTTBRs do not point to the same translation table entries when the other conditions specified for the case when the value of CnP is 1 apply, then the results of translations are CONSTRAINED UNPREDICTABLE, see 'CONSTRAINED UNPREDICTABLE behaviors due to caching of control or data values'. 0b0 The translation table entries pointed to by HTTBR are permitted to differ from corresponding entries for HTTBR for other PEs in the Inner Shareable domain. This is not affected by the value of HTTBR.CnP on those other PEs. 0b1 The translation table entries pointed to by HTTBR are the same as the translation table entries pointed to by HTTBR on every other PE in the Inner Shareable domain for which the value of HTTBR.CnP is 1. AU When FEAT_TTCNP is implemented 0 0 0 Reserved, RES0. Otherwise MRRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <Rt2>, <CRm> if !IsFeatureImplemented(FEAT_AA32EL2) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T2 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x04); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T2 == '1' then AArch32_TakeHypTrapException(0x04); else Undefined(); end; elsif PSTATE.EL == EL2 then R(t, t2) = HTTBR(); elsif PSTATE.EL == EL3 then if SCR().NS == '0' then Undefined(); else R(t, t2) = HTTBR(); end; end; MCRR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <Rt2>, <CRm> if !IsFeatureImplemented(FEAT_AA32EL2) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T2 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x04); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T2 == '1' then AArch32_TakeHypTrapException(0x04); else Undefined(); end; elsif PSTATE.EL == EL2 then HTTBR() = R(t, t2); elsif PSTATE.EL == EL3 then if SCR().NS == '0' then Undefined(); else HTTBR() = R(t, t2); end; end; 2026-03-26 20:27:25 2026-03_rel