<?xml version='1.0' encoding='utf-8'?>
<!DOCTYPE register_page SYSTEM "registers.dtd">
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<register_page>
  <registers>
  
    <register execution_state="AArch32" is_register="True" is_internal="True" is_stub_entry="False">
      <reg_short_name>ICC_BPR0</reg_short_name>
        
        <reg_long_name>Interrupt Controller Binary Point Register 0</reg_long_name>



      
            <reg_condition otherwise="UNDEFINED">when FEAT_AA32EL1 is implemented and GICv3 is implemented</reg_condition>
      




          <reg_reset_value></reg_reset_value>

      <reg_mappings>
        



    
      
      <reg_mapping>
        
  

    

  

    <mapped_name filename="AArch64-icc_bpr0_el1.xml">ICC_BPR0_EL1</mapped_name>
  <mapped_type>Architectural</mapped_type>
      <mapped_execution_state>AArch64</mapped_execution_state>
    <mapped_from_startbit>31</mapped_from_startbit>
    <mapped_from_endbit>0</mapped_from_endbit>
    <mapped_to_startbit>31</mapped_to_startbit>
    <mapped_to_endbit>0</mapped_to_endbit>
    <mapped_from_rangeset output="31:0">
      <range>
        <msb>31</msb>
        <lsb>0</lsb>
      </range>
    </mapped_from_rangeset>
    <mapped_to_rangeset output="31:0">
      <range>
        <msb>31</msb>
        <lsb>0</lsb>
      </range>
    </mapped_to_rangeset>

      </reg_mapping>

      </reg_mappings>

        <reg_purpose>
          
    
      <purpose_text>
        <para>Defines the point at which the priority value fields split into two parts, the group priority field and the subpriority field. The group priority field determines Group 0 interrupt preemption.</para>
      </purpose_text>

        </reg_purpose>

      <reg_groups>
            <reg_group>GIC control registers</reg_group>
            <reg_group>GIC</reg_group>
      </reg_groups>
      
      
        
      <reg_attributes>
          
    
      <attributes_text>
        <para>ICC_BPR0 is a 32-bit register.</para>
      </attributes_text>

      </reg_attributes>
      <reg_fieldsets>
        






<fields id="fieldset_0" length="32">
  <text_before_fields/>
  <field id="fieldset_0-31_3" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False" rwtype="RES0">
    <field_msb>31</field_msb>
    <field_lsb>3</field_lsb>
    <rel_range>31:3</rel_range>
    <field_description order="before"/>
    <field_description order="before">
      <para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para>
    </field_description>
  </field>
  <field id="fieldset_0-2_0" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False">
    <field_name>BinaryPoint</field_name>
    <field_msb>2</field_msb>
    <field_lsb>0</field_lsb>
    <rel_range>2:0</rel_range>
    <field_description order="before"><para>The value of this field controls how the 8-bit interrupt priority field is split into a group priority field, that determines interrupt preemption, and a subpriority field. This is done as follows:</para>
<table><tgroup cols="4"><thead><row><entry>Binary point value</entry><entry>Group priority field</entry><entry>Subpriority field</entry><entry>Field with binary point</entry></row></thead><tbody><row><entry>0</entry><entry>[7:1]</entry><entry>[0]</entry><entry>ggggggg.s</entry></row><row><entry>1</entry><entry>[7:2]</entry><entry>[1:0]</entry><entry>gggggg.ss</entry></row><row><entry>2</entry><entry>[7:3]</entry><entry>[2:0]</entry><entry>ggggg.sss</entry></row><row><entry>3</entry><entry>[7:4]</entry><entry>[3:0]</entry><entry>gggg.ssss</entry></row><row><entry>4</entry><entry>[7:5]</entry><entry>[4:0]</entry><entry>ggg.sssss</entry></row><row><entry>5</entry><entry>[7:6]</entry><entry>[5:0]</entry><entry>gg.ssssss</entry></row><row><entry>6</entry><entry>[7]</entry><entry>[6:0]</entry><entry>g.sssssss</entry></row><row><entry>7</entry><entry>No preemption</entry><entry>[7:0]</entry><entry>.ssssssss</entry></row></tbody></tgroup></table></field_description>
    <field_resets>
      <field_reset reset_type="Warm">
        <field_reset_standard_text>AU</field_reset_standard_text>
      </field_reset>
    </field_resets>
  </field>
  <text_after_fields/>
</fields>




<reg_fieldset length="32">
  <fieldat id="fieldset_0-31_3" msb="31" lsb="3"/>
  <fieldat id="fieldset_0-2_0" msb="2" lsb="0"/>
</reg_fieldset>


      </reg_fieldsets>

      <access_mechanisms>
          


  
    
      <access_permission_text>
        <para>The minimum binary point value is derived from the number of implemented priority bits. The number of priority bits is <arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word>, and reported by <register_link state="AArch32" id="AArch32-icc_ctlr.xml">ICC_CTLR</register_link>.PRIbits and <register_link state="AArch32" id="AArch32-icc_mctlr.xml">ICC_MCTLR</register_link>.PRIbits.</para>

      </access_permission_text>
      <access_permission_text>
        <para>An attempt to program the binary point field to a value less than the minimum value sets the field to the minimum value. On a reset, the binary point field is set to the minimum supported value.</para>
      </access_permission_text>





    
        
        <access_mechanism accessor="MRC ICC_BPR0" type="SystemAccessor">
            <encoding>
            <access_instruction>MRC{&lt;c&gt;}{&lt;q&gt;} &lt;coproc&gt;, {#}&lt;opc1&gt;, &lt;Rt&gt;, &lt;CRn&gt;, &lt;CRm&gt;{, {#}&lt;opc2&gt;}</access_instruction>
                
                <enc n="coproc" v="0b1111"/>
                
                <enc n="opc1" v="0b000"/>
                
                <enc n="CRn" v="0b1100"/>
                
                <enc n="CRm" v="0b1000"/>
                
                <enc n="opc2" v="0b011"/>
            </encoding>
            <access_permission>
                <ps name="MRC" sections="1" secttype="access_permission">
                <pstext>
if !(IsFeatureImplemented(FEAT_AA32EL1) &amp;&amp; IsFeatureImplemented(FEAT_GICv3)) then
    Undefined();
elsif PSTATE.EL == EL0 then
    Undefined();
elsif PSTATE.EL == EL1 then
    if HaveEL(EL3) &amp;&amp; EL3SDDUndefPriority() &amp;&amp; IsFeatureImplemented(FEAT_AA64EL3) &amp;&amp; !ELUsingAArch32(EL3) &amp;&amp; SCR_EL3().FIQ == '1' then
        Undefined();
    elsif HaveEL(EL3) &amp;&amp; EL3SDDUndefPriority() &amp;&amp; IsFeatureImplemented(FEAT_AA32EL3) &amp;&amp; ELUsingAArch32(EL3) &amp;&amp; PSTATE.M != M32_Monitor &amp;&amp; SCR().FIQ == '1' then
        Undefined();
    elsif EL2Enabled() &amp;&amp; IsFeatureImplemented(FEAT_AA64EL2) &amp;&amp; !ELUsingAArch32(EL2) &amp;&amp; HSTR_EL2().T12 == '1' then
        AArch64_AArch32SystemAccessTrap(EL2, 0x03);
    elsif EL2Enabled() &amp;&amp; IsFeatureImplemented(FEAT_AA32EL2) &amp;&amp; ELUsingAArch32(EL2) &amp;&amp; HSTR().T12 == '1' then
        AArch32_TakeHypTrapException(0x03);
    elsif ICC_SRE().SRE == '0' then
        Undefined();
    elsif EL2Enabled() &amp;&amp; IsFeatureImplemented(FEAT_AA64EL2) &amp;&amp; !ELUsingAArch32(EL2) &amp;&amp; ICH_HCR_EL2().TALL0 == '1' then
        AArch64_AArch32SystemAccessTrap(EL2, 0x03);
    elsif EL2Enabled() &amp;&amp; IsFeatureImplemented(FEAT_AA32EL2) &amp;&amp; ELUsingAArch32(EL2) &amp;&amp; ICH_HCR().TALL0 == '1' then
        AArch32_TakeHypTrapException(0x03);
    elsif EL2Enabled() &amp;&amp; IsFeatureImplemented(FEAT_AA64EL2) &amp;&amp; !ELUsingAArch32(EL2) &amp;&amp; HCR_EL2().FMO == '1' then
        R(t) = ICV_BPR0();
    elsif EL2Enabled() &amp;&amp; IsFeatureImplemented(FEAT_AA32EL2) &amp;&amp; ELUsingAArch32(EL2) &amp;&amp; HCR().FMO == '1' then
        R(t) = ICV_BPR0();
    elsif HaveEL(EL3) &amp;&amp; IsFeatureImplemented(FEAT_AA64EL3) &amp;&amp; !ELUsingAArch32(EL3) &amp;&amp; SCR_EL3().FIQ == '1' then
        if EL3SDDUndef() then
            Undefined();
        else
            AArch64_AArch32SystemAccessTrap(EL3, 0x03);
        end;
    elsif HaveEL(EL3) &amp;&amp; IsFeatureImplemented(FEAT_AA32EL3) &amp;&amp; ELUsingAArch32(EL3) &amp;&amp; PSTATE.M != M32_Monitor &amp;&amp; SCR().FIQ == '1' then
        if EL3SDDUndef() then
            Undefined();
        else
            AArch32_TakeMonitorTrapException();
        end;
    else
        R(t) = ICC_BPR0();
    end;
elsif PSTATE.EL == EL2 then
    if HaveEL(EL3) &amp;&amp; EL3SDDUndefPriority() &amp;&amp; IsFeatureImplemented(FEAT_AA64EL3) &amp;&amp; !ELUsingAArch32(EL3) &amp;&amp; SCR_EL3().FIQ == '1' then
        Undefined();
    elsif HaveEL(EL3) &amp;&amp; EL3SDDUndefPriority() &amp;&amp; IsFeatureImplemented(FEAT_AA32EL3) &amp;&amp; ELUsingAArch32(EL3) &amp;&amp; SCR().FIQ == '1' then
        Undefined();
    elsif ICC_HSRE().SRE == '0' then
        Undefined();
    elsif HaveEL(EL3) &amp;&amp; IsFeatureImplemented(FEAT_AA64EL3) &amp;&amp; !ELUsingAArch32(EL3) &amp;&amp; SCR_EL3().FIQ == '1' then
        if EL3SDDUndef() then
            Undefined();
        else
            AArch64_AArch32SystemAccessTrap(EL3, 0x03);
        end;
    elsif HaveEL(EL3) &amp;&amp; IsFeatureImplemented(FEAT_AA32EL3) &amp;&amp; ELUsingAArch32(EL3) &amp;&amp; SCR().FIQ == '1' then
        if EL3SDDUndef() then
            Undefined();
        else
            AArch32_TakeMonitorTrapException();
        end;
    else
        R(t) = ICC_BPR0();
    end;
elsif PSTATE.EL == EL3 then
    if ICC_MSRE().SRE == '0' then
        Undefined();
    else
        R(t) = ICC_BPR0();
    end;
end;
                </pstext>
                </ps>
            </access_permission>
        </access_mechanism>
    
        
        <access_mechanism accessor="MCR ICC_BPR0" type="SystemAccessor">
            <encoding>
            <access_instruction>MCR{&lt;c&gt;}{&lt;q&gt;} &lt;coproc&gt;, {#}&lt;opc1&gt;, &lt;Rt&gt;, &lt;CRn&gt;, &lt;CRm&gt;{, {#}&lt;opc2&gt;}</access_instruction>
                
                <enc n="coproc" v="0b1111"/>
                
                <enc n="opc1" v="0b000"/>
                
                <enc n="CRn" v="0b1100"/>
                
                <enc n="CRm" v="0b1000"/>
                
                <enc n="opc2" v="0b011"/>
            </encoding>
            <access_permission>
                <ps name="MCR" sections="1" secttype="access_permission">
                <pstext>
if !(IsFeatureImplemented(FEAT_AA32EL1) &amp;&amp; IsFeatureImplemented(FEAT_GICv3)) then
    Undefined();
elsif PSTATE.EL == EL0 then
    Undefined();
elsif PSTATE.EL == EL1 then
    if HaveEL(EL3) &amp;&amp; EL3SDDUndefPriority() &amp;&amp; IsFeatureImplemented(FEAT_AA64EL3) &amp;&amp; !ELUsingAArch32(EL3) &amp;&amp; SCR_EL3().FIQ == '1' then
        Undefined();
    elsif HaveEL(EL3) &amp;&amp; EL3SDDUndefPriority() &amp;&amp; IsFeatureImplemented(FEAT_AA32EL3) &amp;&amp; ELUsingAArch32(EL3) &amp;&amp; PSTATE.M != M32_Monitor &amp;&amp; SCR().FIQ == '1' then
        Undefined();
    elsif EL2Enabled() &amp;&amp; IsFeatureImplemented(FEAT_AA64EL2) &amp;&amp; !ELUsingAArch32(EL2) &amp;&amp; HSTR_EL2().T12 == '1' then
        AArch64_AArch32SystemAccessTrap(EL2, 0x03);
    elsif EL2Enabled() &amp;&amp; IsFeatureImplemented(FEAT_AA32EL2) &amp;&amp; ELUsingAArch32(EL2) &amp;&amp; HSTR().T12 == '1' then
        AArch32_TakeHypTrapException(0x03);
    elsif ICC_SRE().SRE == '0' then
        Undefined();
    elsif EL2Enabled() &amp;&amp; IsFeatureImplemented(FEAT_AA64EL2) &amp;&amp; !ELUsingAArch32(EL2) &amp;&amp; ICH_HCR_EL2().TALL0 == '1' then
        AArch64_AArch32SystemAccessTrap(EL2, 0x03);
    elsif EL2Enabled() &amp;&amp; IsFeatureImplemented(FEAT_AA32EL2) &amp;&amp; ELUsingAArch32(EL2) &amp;&amp; ICH_HCR().TALL0 == '1' then
        AArch32_TakeHypTrapException(0x03);
    elsif EL2Enabled() &amp;&amp; IsFeatureImplemented(FEAT_AA64EL2) &amp;&amp; !ELUsingAArch32(EL2) &amp;&amp; HCR_EL2().FMO == '1' then
        ICV_BPR0() = R(t);
    elsif EL2Enabled() &amp;&amp; IsFeatureImplemented(FEAT_AA32EL2) &amp;&amp; ELUsingAArch32(EL2) &amp;&amp; HCR().FMO == '1' then
        ICV_BPR0() = R(t);
    elsif HaveEL(EL3) &amp;&amp; IsFeatureImplemented(FEAT_AA64EL3) &amp;&amp; !ELUsingAArch32(EL3) &amp;&amp; SCR_EL3().FIQ == '1' then
        if EL3SDDUndef() then
            Undefined();
        else
            AArch64_AArch32SystemAccessTrap(EL3, 0x03);
        end;
    elsif HaveEL(EL3) &amp;&amp; IsFeatureImplemented(FEAT_AA32EL3) &amp;&amp; ELUsingAArch32(EL3) &amp;&amp; PSTATE.M != M32_Monitor &amp;&amp; SCR().FIQ == '1' then
        if EL3SDDUndef() then
            Undefined();
        else
            AArch32_TakeMonitorTrapException();
        end;
    else
        ICC_BPR0() = R(t);
    end;
elsif PSTATE.EL == EL2 then
    if HaveEL(EL3) &amp;&amp; EL3SDDUndefPriority() &amp;&amp; IsFeatureImplemented(FEAT_AA64EL3) &amp;&amp; !ELUsingAArch32(EL3) &amp;&amp; SCR_EL3().FIQ == '1' then
        Undefined();
    elsif HaveEL(EL3) &amp;&amp; EL3SDDUndefPriority() &amp;&amp; IsFeatureImplemented(FEAT_AA32EL3) &amp;&amp; ELUsingAArch32(EL3) &amp;&amp; SCR().FIQ == '1' then
        Undefined();
    elsif ICC_HSRE().SRE == '0' then
        Undefined();
    elsif HaveEL(EL3) &amp;&amp; IsFeatureImplemented(FEAT_AA64EL3) &amp;&amp; !ELUsingAArch32(EL3) &amp;&amp; SCR_EL3().FIQ == '1' then
        if EL3SDDUndef() then
            Undefined();
        else
            AArch64_AArch32SystemAccessTrap(EL3, 0x03);
        end;
    elsif HaveEL(EL3) &amp;&amp; IsFeatureImplemented(FEAT_AA32EL3) &amp;&amp; ELUsingAArch32(EL3) &amp;&amp; SCR().FIQ == '1' then
        if EL3SDDUndef() then
            Undefined();
        else
            AArch32_TakeMonitorTrapException();
        end;
    else
        ICC_BPR0() = R(t);
    end;
elsif PSTATE.EL == EL3 then
    if ICC_MSRE().SRE == '0' then
        Undefined();
    else
        ICC_BPR0() = R(t);
    end;
end;
                </pstext>
                </ps>
            </access_permission>
        </access_mechanism>

      </access_mechanisms>

      <arch_variants>
      </arch_variants>
  </register>
</registers>
<timestamp>2026-03-26 20:27:25</timestamp>
<commit_id>2026-03_rel</commit_id>
</register_page>