ICC_BPR1
Interrupt Controller Binary Point Register 1
when FEAT_AA32EL1 is implemented and GICv3 is implemented
ICC_BPR1_EL1
Architectural
AArch64
31
0
ICC_BPR1_S
31
0
ICC_BPR1_EL1_S
31
0
31
0
ICC_BPR1_EL1
Architectural
AArch64
31
0
ICC_BPR1_NS
31
0
ICC_BPR1_EL1_NS
31
0
31
0
Defines the point at which the priority value fields split into two parts, the group priority field and the subpriority field. The group priority field determines Group 1 interrupt preemption.
GIC control registers
GIC
In GIC implementations supporting two Security states, this register is Banked.
This register is banked between ICC_BPR1 and ICC_BPR1_S and ICC_BPR1_NS.
ICC_BPR1 is a 32-bit register.
This register has the following instances:
ICC_BPR1, when EL3 is not implemented or FEAT_AA64 is implemented.
ICC_BPR1_S, when FEAT_AA32EL3 is implemented.
ICC_BPR1_NS, when FEAT_AA32EL3 is implemented.
31
3
31:3
Reserved, RES0.
BinaryPoint
2
0
2:0
If the GIC is configured to use separate binary point fields for Group 0 and Group 1 interrupts, the value of this field controls how the 8-bit interrupt priority field is split into a group priority field, that determines interrupt preemption, and a subpriority field. For more information about priorities, see 'Priority grouping' in ARM® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0 (ARM IHI 0069).
Writing 0 to this field will set this field to its reset value.
If EL3 is implemented and ICC_MCTLR.CBPR_EL1S is 1:
Accesses to this register at EL3 not in Monitor mode access the state of ICC_BPR0.
When SCR_EL3.EEL2 is 1 and HCR_EL2.IMO is 1, Secure accesses to this register at EL1 access the state of ICV_BPR1.
Otherwise, Secure accesses to this register at EL1 access the state of ICC_BPR0.
If EL3 is implemented and ICC_MCTLR.CBPR_EL1NS is 1, Non-secure accesses to this register at EL1 and EL2 behave as follows, depending on the values of HCR.IMO and SCR.IRQ:
HCR.IMOSCR_IRQBehavior
0b00b0Non-secure EL1 and EL2 reads return ICC_BPR0 + 1 saturated to 0b111. Non-secure EL1 and EL2 writes are ignored.
0b00b1Non-secure EL1 and EL2 accesses trap to EL3.
0b10b0Non-secure EL1 accesses affect virtual interrupts. Non-secure EL2 reads return ICC_BPR0 + 1 saturated to 0b111. Non-secure EL2 writes ignored.
0b10b1Non-secure EL1 accesses affect virtual interrupts. Non-secure EL2 accesses trap to EL3.
If EL3 is not implemented and ICC_CTLR.CBPR is 1, Non-secure accesses to this register at EL1 and EL2 behave as follows, depending on the values of HCR.IMO:
HCR.IMOBehavior
0b0Non-secure EL1 and EL2 reads return ICC_BPR0 + 1 saturated to 0b111. Non-secure EL1 and EL2 writes are ignored.
0b1Non-secure EL1 accesses affect virtual interrupts. Non-secure EL2 reads return ICC_BPR0 + 1 saturated to 0b111. Non-secure EL2 writes are ignored.
This field resets to an IMPLEMENTATION DEFINED nonzero value.
When the PE resets into an Exception level that is using AArch32, the reset value is equal to:
For the Secure copy of the register, the minimum value of ICC_BPR0 plus one.
For the Non-secure copy of the register, the minimum value of ICC_BPR0.
Where the minimum value of ICC_BPR0 is IMPLEMENTATION DEFINED.
If EL3 is not implemented:
If the PE is Secure this reset value is (minimum value of ICC_BPR0 plus one).
If the PE is Non-secure this reset value is (minimum value of ICC_BPR0).
An attempt to program the binary point field to a value less than the reset value sets the field to the reset value.
MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
if !(IsFeatureImplemented(FEAT_AA32EL1) && IsFeatureImplemented(FEAT_GICv3)) then
Undefined();
elsif PSTATE.EL == EL0 then
Undefined();
elsif PSTATE.EL == EL1 then
if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && SCR_EL3().IRQ == '1' then
Undefined();
elsif HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) && PSTATE.M != M32_Monitor && SCR().IRQ == '1' then
Undefined();
elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T12 == '1' then
AArch64_AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T12 == '1' then
AArch32_TakeHypTrapException(0x03);
elsif ICC_SRE().SRE == '0' then
Undefined();
elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && ICH_HCR_EL2().TALL1 == '1' then
AArch64_AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && ICH_HCR().TALL1 == '1' then
AArch32_TakeHypTrapException(0x03);
elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HCR_EL2().IMO == '1' then
R(t) = ICV_BPR1();
elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HCR().IMO == '1' then
R(t) = ICV_BPR1();
elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && SCR_EL3().IRQ == '1' then
if EL3SDDUndef() then
Undefined();
else
AArch64_AArch32SystemAccessTrap(EL3, 0x03);
end;
elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) && PSTATE.M != M32_Monitor && SCR().IRQ == '1' then
if EL3SDDUndef() then
Undefined();
else
AArch32_TakeMonitorTrapException();
end;
elsif HaveEL(EL3) then
R(t) = ICC_BPR1_NS();
else
R(t) = ICC_BPR1();
end;
elsif PSTATE.EL == EL2 then
if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && SCR_EL3().IRQ == '1' then
Undefined();
elsif HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) && SCR().IRQ == '1' then
Undefined();
elsif ICC_HSRE().SRE == '0' then
Undefined();
elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && SCR_EL3().IRQ == '1' then
if EL3SDDUndef() then
Undefined();
else
AArch64_AArch32SystemAccessTrap(EL3, 0x03);
end;
elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) && SCR().IRQ == '1' then
if EL3SDDUndef() then
Undefined();
else
AArch32_TakeMonitorTrapException();
end;
elsif HaveEL(EL3) then
R(t) = ICC_BPR1_NS();
else
R(t) = ICC_BPR1();
end;
elsif PSTATE.EL == EL3 then
if ICC_MSRE().SRE == '0' then
Undefined();
else
if EffectiveSCR_EL3_NS() == '0' then
R(t) = ICC_BPR1_S();
else
R(t) = ICC_BPR1_NS();
end;
end;
end;
MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
if !(IsFeatureImplemented(FEAT_AA32EL1) && IsFeatureImplemented(FEAT_GICv3)) then
Undefined();
elsif PSTATE.EL == EL0 then
Undefined();
elsif PSTATE.EL == EL1 then
if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && SCR_EL3().IRQ == '1' then
Undefined();
elsif HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) && PSTATE.M != M32_Monitor && SCR().IRQ == '1' then
Undefined();
elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T12 == '1' then
AArch64_AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T12 == '1' then
AArch32_TakeHypTrapException(0x03);
elsif ICC_SRE().SRE == '0' then
Undefined();
elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && ICH_HCR_EL2().TALL1 == '1' then
AArch64_AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && ICH_HCR().TALL1 == '1' then
AArch32_TakeHypTrapException(0x03);
elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HCR_EL2().IMO == '1' then
ICV_BPR1() = R(t);
elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HCR().IMO == '1' then
ICV_BPR1() = R(t);
elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && SCR_EL3().IRQ == '1' then
if EL3SDDUndef() then
Undefined();
else
AArch64_AArch32SystemAccessTrap(EL3, 0x03);
end;
elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) && PSTATE.M != M32_Monitor && SCR().IRQ == '1' then
if EL3SDDUndef() then
Undefined();
else
AArch32_TakeMonitorTrapException();
end;
elsif HaveEL(EL3) then
ICC_BPR1_NS() = R(t);
else
ICC_BPR1() = R(t);
end;
elsif PSTATE.EL == EL2 then
if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && SCR_EL3().IRQ == '1' then
Undefined();
elsif HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) && SCR().IRQ == '1' then
Undefined();
elsif ICC_HSRE().SRE == '0' then
Undefined();
elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && SCR_EL3().IRQ == '1' then
if EL3SDDUndef() then
Undefined();
else
AArch64_AArch32SystemAccessTrap(EL3, 0x03);
end;
elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) && SCR().IRQ == '1' then
if EL3SDDUndef() then
Undefined();
else
AArch32_TakeMonitorTrapException();
end;
elsif HaveEL(EL3) then
ICC_BPR1_NS() = R(t);
else
ICC_BPR1() = R(t);
end;
elsif PSTATE.EL == EL3 then
if ICC_MSRE().SRE == '0' then
Undefined();
else
if EffectiveSCR_EL3_NS() == '0' then
ICC_BPR1_S() = R(t);
else
ICC_BPR1_NS() = R(t);
end;
end;
end;
2026-03-26 20:27:25
2026-03_rel