ICC_CTLR Interrupt Controller Control Register when FEAT_AA32EL1 is implemented and GICv3 is implemented ICC_CTLR_EL1 Architectural AArch64 31 0 ICC_CTLR_S 31 0 ICC_CTLR_EL1_S 31 0 31 0 ICC_CTLR_EL1 Architectural AArch64 31 0 ICC_CTLR_NS 31 0 ICC_CTLR_EL1_NS 31 0 31 0 Controls aspects of the behavior of the GIC CPU interface and provides information about the features implemented. GIC control registers GIC This register is banked between ICC_CTLR and ICC_CTLR_S and ICC_CTLR_NS. ICC_CTLR is a 32-bit register. This register has the following instances: ICC_CTLR, when EL3 is not implemented or FEAT_AA64 is implemented. ICC_CTLR_S, when FEAT_AA32EL3 is implemented. ICC_CTLR_NS, when FEAT_AA32EL3 is implemented. 31 20 31:20 Reserved, RES0. ExtRange 19 19 19 Extended INTID range. If EL3 is implemented, ICC_CTLR_EL1.ExtRange is an alias of ICC_CTLR_EL3.ExtRange. 0b0 CPU interface does not support INTIDs in the range 1024..8191. Behavior is UNPREDICTABLE if the IRI delivers an interrupt in the range 1024 to 8191 to the CPU interface. Arm strongly recommends that the IRI is not configured to deliver interrupts in this range to a PE that does not support them. 0b1 CPU interface supports INTIDs in the range 1024..8191. All INTIDs in the range 1024..8191 are treated as requiring deactivation. RO RSS 18 18 18 Range Selector Support. 0b0 Targeted SGIs with affinity level 0 values of 0 - 15 are supported. 0b1 Targeted SGIs with affinity level 0 values of 0 - 255 are supported. RO 17 16 17:16 Reserved, RES0. A3V 15 15 15 Affinity 3 Valid. If EL3 is implemented and using AArch32, this bit is an alias of ICC_MCTLR.A3V. If EL3 is implemented and using AArch64, this bit is an alias of ICC_CTLR_EL3.A3V. 0b0 The CPU interface logic only supports zero values of Affinity 3 in SGI generation System registers. 0b1 The CPU interface logic supports nonzero values of Affinity 3 in SGI generation System registers. RO SEIS 14 14 14 SEI Support. Indicates whether the CPU interface supports local generation of SEIs. If EL3 is implemented and using AArch32, this bit is an alias of ICC_MCTLR.SEIS. If EL3 is implemented and using AArch64, this bit is an alias of ICC_CTLR_EL3.SEIS. 0b0 The CPU interface logic does not support local generation of SEIs. 0b1 The CPU interface logic supports local generation of SEIs. RO IDbits 13 11 13:11 Identifier bits. The number of physical interrupt identifier bits supported. All other values are reserved. If EL3 is implemented and using AArch32, this field is an alias of ICC_MCTLR.IDbits. If EL3 is implemented and using AArch64, this field is an alias of ICC_CTLR_EL3.IDbits. 0b000 16 bits. 0b001 24 bits. RO PRIbits 10 8 10:8 Priority bits. The number of priority bits implemented, minus one. An implementation that supports two Security states must implement at least 32 levels of physical priority (5 priority bits). An implementation that supports only a single Security state must implement at least 16 levels of physical priority (4 priority bits). This field always returns the number of priority bits implemented, regardless of the Security state of the access or the value of GICD_CTLR.DS.The division between group priority and subpriority is defined in the binary point registers ICC_BPR0 and ICC_BPR1. If EL3 is implemented and using AArch32, physical accesses return the value from ICC_MCTLR.PRIbits. If EL3 is implemented and using AArch64, physical accesses return the value from ICC_CTLR_EL3.PRIbits. If EL3 is not implemented, physical accesses return the value from this field. This field has an IMPLEMENTATION DEFINED value. RO 7 7 7 Reserved, RES0. PMHE 6 6 6 Priority Mask Hint Enable. Controls whether the priority mask register is used as a hint for interrupt distribution: If EL3 is implemented: If EL3 is using AArch32, this bit is an alias of ICC_MCTLR.PMHE. If EL3 is using AArch64, this bit is an alias of ICC_CTLR_EL3.PMHE. If GICD_CTLR.DS == 0, this bit is read-only. If GICD_CTLR.DS == 1, this bit is read/write. If EL3 is not implemented, it is IMPLEMENTATION DEFINED whether this bit is read-only or read/write: If this bit is read-only, an implementation can choose to make this field RAZ/WI or RAO/WI. If this bit is read/write, it resets to zero. 0b0 Disables use of ICC_PMR as a hint for interrupt distribution. 0b1 Enables use of ICC_PMR as a hint for interrupt distribution. 5 2 5:2 Reserved, RES0. EOImode 1 1 1 EOI mode for the current Security state. Controls whether a write to an End of Interrupt register also deactivates the interrupt: If EL3 is implemented: If EL3 is using AArch32, this bit is an alias of ICC_MCTLR.EOImode_EL1{S, NS} where S or NS corresponds to the current Security state. If EL3 is using AArch64, this bit is an alias of ICC_CTLR_EL3.EOImode_EL1{S, NS} where S or NS corresponds to the current Security state. If EL3 is not implemented, it is IMPLEMENTATION DEFINED whether this bit is read-only or read/write: If this bit is read-only, an implementation can choose to make this field RAZ/WI or RAO/WI. If this bit is read/write, it resets to zero. 0b0 ICC_EOIR0 and ICC_EOIR1 provide both priority drop and interrupt deactivation functionality. Accesses to ICC_DIR are UNPREDICTABLE. 0b1 ICC_EOIR0 and ICC_EOIR1 provide priority drop functionality only. ICC_DIR provides interrupt deactivation functionality. CBPR 0 0 0 Common Binary Point Register. Controls whether the same register is used for interrupt preemption of both Group 0 and Group 1 interrupts: If EL3 is implemented: If EL3 is using AArch32, this bit is an alias of ICC_MCTLR.CBPR_EL1{S,NS} where S or NS corresponds to the current Security state. If EL3 is using AArch64, this bit is an alias of ICC_CTLR_EL3.CBPR_EL1{S,NS} where S or NS corresponds to the current Security state. If GICD_CTLR.DS == 0, this bit is read-only. If GICD_CTLR.DS == 1, this bit is read/write. If EL3 is not implemented, it is IMPLEMENTATION DEFINED whether this bit is read-only or read/write: If this bit is read-only, an implementation can choose to make this field RAZ/WI or RAO/WI. If this bit is read/write, it resets to zero. 0b0 ICC_BPR0 determines the preemption group for Group 0 interrupts only. ICC_BPR1 determines the preemption group for Group 1 interrupts. 0b1 ICC_BPR0 determines the preemption group for both Group 0 and Group 1 interrupts. MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>} if !(IsFeatureImplemented(FEAT_AA32EL1) && IsFeatureImplemented(FEAT_GICv3)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && SCR_EL3().[IRQ,FIQ] == '11' then Undefined(); elsif HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) && PSTATE.M != M32_Monitor && SCR().[IRQ,FIQ] == '11' then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T12 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T12 == '1' then AArch32_TakeHypTrapException(0x03); elsif ICC_SRE().SRE == '0' then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && ICH_HCR_EL2().TC == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && ICH_HCR().TC == '1' then AArch32_TakeHypTrapException(0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HCR_EL2().FMO == '1' then R(t) = ICV_CTLR(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HCR_EL2().IMO == '1' then R(t) = ICV_CTLR(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HCR().FMO == '1' then R(t) = ICV_CTLR(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HCR().IMO == '1' then R(t) = ICV_CTLR(); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && SCR_EL3().[IRQ,FIQ] == '11' then if EL3SDDUndef() then Undefined(); else AArch64_AArch32SystemAccessTrap(EL3, 0x03); end; elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) && PSTATE.M != M32_Monitor && SCR().[IRQ,FIQ] == '11' then if EL3SDDUndef() then Undefined(); else AArch32_TakeMonitorTrapException(); end; elsif HaveEL(EL3) then R(t) = ICC_CTLR_NS(); else R(t) = ICC_CTLR(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && SCR_EL3().[IRQ,FIQ] == '11' then Undefined(); elsif HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) && SCR().[IRQ,FIQ] == '11' then Undefined(); elsif ICC_HSRE().SRE == '0' then Undefined(); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && SCR_EL3().[IRQ,FIQ] == '11' then if EL3SDDUndef() then Undefined(); else AArch64_AArch32SystemAccessTrap(EL3, 0x03); end; elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) && SCR().[IRQ,FIQ] == '11' then if EL3SDDUndef() then Undefined(); else AArch32_TakeMonitorTrapException(); end; elsif HaveEL(EL3) then R(t) = ICC_CTLR_NS(); else R(t) = ICC_CTLR(); end; elsif PSTATE.EL == EL3 then if ICC_MSRE().SRE == '0' then Undefined(); else if EffectiveSCR_EL3_NS() == '0' then R(t) = ICC_CTLR_S(); else R(t) = ICC_CTLR_NS(); end; end; end; MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>} if !(IsFeatureImplemented(FEAT_AA32EL1) && IsFeatureImplemented(FEAT_GICv3)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && SCR_EL3().[IRQ,FIQ] == '11' then Undefined(); elsif HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) && PSTATE.M != M32_Monitor && SCR().[IRQ,FIQ] == '11' then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T12 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T12 == '1' then AArch32_TakeHypTrapException(0x03); elsif ICC_SRE().SRE == '0' then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && ICH_HCR_EL2().TC == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && ICH_HCR().TC == '1' then AArch32_TakeHypTrapException(0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HCR_EL2().FMO == '1' then ICV_CTLR() = R(t); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HCR_EL2().IMO == '1' then ICV_CTLR() = R(t); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HCR().FMO == '1' then ICV_CTLR() = R(t); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HCR().IMO == '1' then ICV_CTLR() = R(t); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && SCR_EL3().[IRQ,FIQ] == '11' then if EL3SDDUndef() then Undefined(); else AArch64_AArch32SystemAccessTrap(EL3, 0x03); end; elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) && PSTATE.M != M32_Monitor && SCR().[IRQ,FIQ] == '11' then if EL3SDDUndef() then Undefined(); else AArch32_TakeMonitorTrapException(); end; elsif HaveEL(EL3) then ICC_CTLR_NS() = R(t); else ICC_CTLR() = R(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && SCR_EL3().[IRQ,FIQ] == '11' then Undefined(); elsif HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) && SCR().[IRQ,FIQ] == '11' then Undefined(); elsif ICC_HSRE().SRE == '0' then Undefined(); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && SCR_EL3().[IRQ,FIQ] == '11' then if EL3SDDUndef() then Undefined(); else AArch64_AArch32SystemAccessTrap(EL3, 0x03); end; elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) && SCR().[IRQ,FIQ] == '11' then if EL3SDDUndef() then Undefined(); else AArch32_TakeMonitorTrapException(); end; elsif HaveEL(EL3) then ICC_CTLR_NS() = R(t); else ICC_CTLR() = R(t); end; elsif PSTATE.EL == EL3 then if ICC_MSRE().SRE == '0' then Undefined(); else if EffectiveSCR_EL3_NS() == '0' then ICC_CTLR_S() = R(t); else ICC_CTLR_NS() = R(t); end; end; end; 2026-03-26 20:27:25 2026-03_rel