ICC_HSRE Interrupt Controller Hyp System Register Enable register when FEAT_AA32EL2 is implemented, GICv3 is implemented, and (EL2 is implemented or EL3 is implemented) ICC_SRE_EL2 Architectural AArch64 31 0 31 0 31 0 31 0 Controls whether the System register interface or the memory-mapped interface to the GIC CPU interface is used for EL2. GIC control registers GIC Virt ICC_HSRE is a 32-bit register. 31 4 31:4 Reserved, RES0. Enable 3 3 3 Enable. Enables lower Exception level access to ICC_SRE. If ICC_HSRE.SRE is RAO/WI, an implementation is permitted to make the Enable bit RAO/WI. If ICC_HSRE.SRE is 0, the Enable bit behaves as 1 for all purposes other than reading the value of the bit. 0b0 Non-secure EL1 accesses to ICC_SRE trap to EL2. 0b1 Non-secure EL1 accesses to ICC_SRE do not trap to EL2. AU DIB 2 2 2 Disable IRQ bypass. If EL3 is implemented and GICD_CTLR.DS is 0, this field is a read-only alias of ICC_MSRE.DIB. If EL3 is implemented and GICD_CTLR.DS is 1, this field is a read/write alias of ICC_MSRE.DIB. In systems that do not support IRQ bypass, this bit is RAO/WI. 0b0 IRQ bypass enabled. 0b1 IRQ bypass disabled. '0' DFB 1 1 1 Disable FIQ bypass. If EL3 is implemented and GICD_CTLR.DS is 0, this field is a read-only alias of ICC_MSRE.DFB. If EL3 is implemented and GICD_CTLR.DS is 1, this field is a read/write alias of ICC_MSRE.DFB. In systems that do not support FIQ bypass, this bit is RAO/WI. 0b0 FIQ bypass enabled. 0b1 FIQ bypass disabled. '0' SRE 0 0 0 System Register Enable. If software changes this bit from 1 to 0, the results are UNPREDICTABLE. If an implementation supports only a System register interface to the GIC CPU interface, this bit is RAO/WI. If EL3 is implemented and using AArch64: When ICC_SRE_EL3.SRE==0 this bit is RAZ/WI. If EL3 is implemented using AArch32: When ICC_MSRE.SRE==0 this bit is RAZ/WI. 0b0 The memory-mapped interface must be used. Accesses at EL2 or below to any ICH_* System register, or any EL1 or EL2 ICC_* register other than ICC_SRE or ICC_HSRE, are UNDEFINED. 0b1 The System register interface to the ICH_* registers and the EL1 and EL2 ICC_* registers is enabled for EL2. '0' The GIC architecture permits, but does not require, that registers can be shared between memory-mapped registers and the equivalent System registers. This means that if the memory-mapped registers have been accessed while ICC_HSRE.SRE==0, then the System registers might be modified. Therefore, software must only rely on the reset values of the System registers if there has been no use of the GIC functionality while the memory-mapped registers are in use. Otherwise, the System register values must be treated as UNKNOWN. MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>} if !(IsFeatureImplemented(FEAT_AA32EL2) && IsFeatureImplemented(FEAT_GICv3) && (HaveEL(EL2) || HaveEL(EL3))) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T12 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T12 == '1' then AArch32_TakeHypTrapException(0x03); else Undefined(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && ICC_SRE_EL3().Enable == '0' then Undefined(); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && ICC_SRE_EL3().Enable == '0' then if EL3SDDUndef() then Undefined(); else AArch64_AArch32SystemAccessTrap(EL3, 0x03); end; elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) && ICC_MSRE().Enable == '0' then Undefined(); else R(t) = ICC_HSRE(); end; elsif PSTATE.EL == EL3 then if !EL2Enabled() then Undefined(); else R(t) = ICC_HSRE(); end; end; MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>} if !(IsFeatureImplemented(FEAT_AA32EL2) && IsFeatureImplemented(FEAT_GICv3) && (HaveEL(EL2) || HaveEL(EL3))) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T12 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T12 == '1' then AArch32_TakeHypTrapException(0x03); else Undefined(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && ICC_SRE_EL3().Enable == '0' then Undefined(); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && ICC_SRE_EL3().Enable == '0' then if EL3SDDUndef() then Undefined(); else AArch64_AArch32SystemAccessTrap(EL3, 0x03); end; elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) && ICC_MSRE().Enable == '0' then Undefined(); else ICC_HSRE() = R(t); end; elsif PSTATE.EL == EL3 then if !EL2Enabled() then Undefined(); else ICC_HSRE() = R(t); end; end; 2026-03-26 20:27:25 2026-03_rel