ICC_MCTLR Interrupt Controller Monitor Control Register when FEAT_AA32EL3 is implemented, GICv3 is implemented, and EL3 is implemented Controls aspects of the behavior of the GIC CPU interface and provides information about the features implemented. GIC control registers Secure GIC ICC_MCTLR is a 32-bit register. 31 20 31:20 Reserved, RES0. ExtRange 19 19 19 Extended INTID range (read-only). 0b0 CPU interface does not support INTIDs in the range 1024..8191. Behavior is UNPREDICTABLE if the IRI delivers an interrupt in the range 1024 to 8191 to the CPU interface. Arm strongly recommends that the IRI is not configured to deliver interrupts in this range to a PE that does not support them. 0b1 CPU interface supports INTIDs in the range 1024..8191 All INTIDs in the range 1024..8191 are treated as requiring deactivation. RSS 18 18 18 Range Selector Support. Possible values are: This bit is read-only. 0b0 Targeted SGIs with affinity level 0 values of 0 - 15 are supported. 0b1 Targeted SGIs with affinity level 0 values of 0 - 255 are supported. nDS 17 17 17 Disable Security not supported. Read-only and writes are ignored. 0b0 The CPU interface logic supports disabling of security. 0b1 The CPU interface logic does not support disabling of security, and requires that security is not disabled. 16 16 16 Reserved, RES0. A3V 15 15 15 Affinity 3 Valid. Read-only and writes are ignored. If EL3 is present, ICC_CTLR.A3V is an alias of ICC_MCTLR.A3V 0b0 The CPU interface logic does not support nonzero values of the Aff3 field in SGI generation System registers. 0b1 The CPU interface logic supports nonzero values of the Aff3 field in SGI generation System registers. SEIS 14 14 14 SEI Support. Read-only and writes are ignored. Indicates whether the CPU interface supports generation of SEIs. If EL3 is present, ICC_CTLR.SEIS is an alias of ICC_MCTLR.SEIS 0b0 The CPU interface logic does not support generation of SEIs. 0b1 The CPU interface logic supports generation of SEIs. IDbits 13 11 13:11 Identifier bits. Read-only and writes are ignored. Indicates the number of physical interrupt identifier bits supported. All other values are reserved. If EL3 is present, ICC_CTLR.IDbits is an alias of ICC_MCTLR.IDbits 0b000 16 bits. 0b001 24 bits. PRIbits 10 8 10:8 Priority bits. Read-only and writes are ignored. The number of priority bits implemented, minus one. An implementation that supports two Security states must implement at least 32 levels of physical priority (5 priority bits). An implementation that supports only a single Security state must implement at least 16 levels of physical priority (4 priority bits). This field always returns the number of priority bits implemented, regardless of the value of SCR.NS or the value of GICD_CTLR.DS.The division between group priority and subpriority is defined in the binary point registers ICC_BPR0 and ICC_BPR1. This field determines the minimum value of ICC_BPR0. 7 7 7 Reserved, RES0. PMHE 6 6 6 Priority Mask Hint Enable. Software must write ICC_PMR to 0xFF before clearing this field to 0. An implementation might choose to make this field RAO/WI. If EL3 is present, ICC_CTLR.PMHE is an alias of ICC_MCTLR.PMHE. 0b0 Disables use of the priority mask register as a hint for interrupt distribution. 0b1 Enables use of the priority mask register as a hint for interrupt distribution. '0' RM 5 5 5 SBZ. The equivalent bit in AArch64 is the Routing Modifier bit. This feature is not supported when EL3 is using AArch32. AU EOImode_EL1NS 4 4 4 EOI mode for interrupts handled at Non-secure EL1 and EL2. Controls whether a write to an End of Interrupt register also deactivates the interrupt. If EL3 is present, ICC_CTLR(NS).EOImode is an alias of ICC_MCTLR.EOImode_EL1NS. 0b0 ICC_EOIR0 and ICC_EOIR1 provide both priority drop and interrupt deactivation functionality. Accesses to ICC_DIR are UNPREDICTABLE. 0b1 ICC_EOIR0 and ICC_EOIR1 provide priority drop functionality only. ICC_DIR provides interrupt deactivation functionality. AU EOImode_EL1S 3 3 3 EOI mode for interrupts handled at Secure EL1. Controls whether a write to an End of Interrupt register also deactivates the interrupt. If EL3 is present, ICC_CTLR(S).EOImode is an alias of ICC_MCTLR.EOImode_EL1S. 0b0 ICC_EOIR0 and ICC_EOIR1 provide both priority drop and interrupt deactivation functionality. Accesses to ICC_DIR are UNPREDICTABLE. 0b1 ICC_EOIR0 and ICC_EOIR1 provide priority drop functionality only. ICC_DIR provides interrupt deactivation functionality. AU EOImode_EL3 2 2 2 EOI mode for interrupts handled at EL3. Controls whether a write to an End of Interrupt register also deactivates the interrupt. 0b0 ICC_EOIR0 and ICC_EOIR1 provide both priority drop and interrupt deactivation functionality. Accesses to ICC_DIR are UNPREDICTABLE. 0b1 ICC_EOIR0 and ICC_EOIR1 provide priority drop functionality only. ICC_DIR provides interrupt deactivation functionality. AU CBPR_EL1NS 1 1 1 Common Binary Point Register, EL1 Non-secure. Controls whether the same register is used for interrupt preemption of both Group 0 and Group 1 Non-secure interrupts at EL1 and EL2. If EL3 is present, ICC_CTLR(NS).CBPR is an alias of ICC_MCTLR.CBPR_EL1NS. 0b0 ICC_BPR0 determines the preemption group for Group 0 interrupts only. ICC_BPR1 determines the preemption group for Non-secure Group 1 interrupts. 0b1 ICC_BPR0 determines the preemption group for Group 0 interrupts and Non-secure Group 1 interrupts. Non-secure accesses to GICC_BPR and ICC_BPR1 access the state of ICC_BPR0. AU CBPR_EL1S 0 0 0 Common Binary Point Register, EL1 Secure. Controls whether the same register is used for interrupt preemption of both Group 0 and Group 1 Secure interrupts in Secure non-Monitor modes. If EL3 is present, ICC_CTLR(S).CBPR is an alias of ICC_MCTLR.CBPR_EL1S. 0b0 ICC_BPR0 determines the preemption group for Group 0 interrupts only. ICC_BPR1 determines the preemption group for Secure Group 1 interrupts. 0b1 ICC_BPR0 determines the preemption group for Group 0 interrupts and Secure Group 1 interrupts. Secure EL1 accesses, or EL3 accesses when not in Monitor mode, to ICC_BPR1 access the state of ICC_BPR0. AU This register is only accessible when executing in Monitor mode. MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>} if !(IsFeatureImplemented(FEAT_AA32EL3) && IsFeatureImplemented(FEAT_GICv3) && HaveEL(EL3)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T12 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T12 == '1' then AArch32_TakeHypTrapException(0x03); else Undefined(); end; elsif PSTATE.EL == EL2 then Undefined(); elsif PSTATE.EL == EL3 then if ICC_MSRE().SRE == '0' then Undefined(); else R(t) = ICC_MCTLR(); end; end; MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>} if !(IsFeatureImplemented(FEAT_AA32EL3) && IsFeatureImplemented(FEAT_GICv3) && HaveEL(EL3)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T12 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T12 == '1' then AArch32_TakeHypTrapException(0x03); else Undefined(); end; elsif PSTATE.EL == EL2 then Undefined(); elsif PSTATE.EL == EL3 then if ICC_MSRE().SRE == '0' then Undefined(); else ICC_MCTLR() = R(t); end; end; 2026-03-26 20:27:25 2026-03_rel