ICC_MSRE Interrupt Controller Monitor System Register Enable register when FEAT_AA32EL3 is implemented, GICv3 is implemented, and EL3 is implemented Controls whether the System register interface or the memory-mapped interface to the GIC CPU interface is used for EL3. GIC control registers Secure GIC ICC_MSRE is a 32-bit register. 31 4 31:4 Reserved, RES0. Enable 3 3 3 Enable. Enables lower Exception level access to ICC_SRE and ICC_HSRE. If ICC_MSRE.SRE is RAO/WI, an implementation is permitted to make the Enable bit RAO/WI. If ICC_MSRE.SRE is 0, the Enable bit behaves as 1 for all purposes other than reading the value of the bit. 0b0 Secure EL1 accesses to Secure ICC_SRE trap to EL3. EL2 accesses to Non-secure ICC_SRE and ICC_HSRE trap to EL3. Non-secure EL1 accesses to ICC_SRE trap to EL3, unless these accesses are trapped to EL2 as a result of ICC_HSRE.Enable == 0. 0b1 Secure EL1 accesses to Secure ICC_SRE do not trap to EL3. EL2 accesses to Non-secure ICC_SRE and ICC_HSRE do not trap to EL3. Non-secure EL1 accesses to ICC_SRE do not trap to EL3. AU DIB 2 2 2 Disable IRQ bypass. In systems that do not support IRQ bypass, this bit is RAO/WI. 0b0 IRQ bypass enabled. 0b1 IRQ bypass disabled. '0' DFB 1 1 1 Disable FIQ bypass. In systems that do not support FIQ bypass, this bit is RAO/WI. 0b0 FIQ bypass enabled. 0b1 FIQ bypass disabled. '0' SRE 0 0 0 System Register Enable. If software changes this bit from 1 to 0, the results are UNPREDICTABLE. If an implementation supports only a System register interface to the GIC CPU interface, this bit is RAO/WI. 0b0 The memory-mapped interface must be used. Accesses at EL3 or below to any ICH_* System register, or any EL1, EL2, or EL3 ICC_* register other than ICC_SRE, ICC_HSRE, or ICC_MSRE, are UNDEFINED. 0b1 The System register interface to the ICH_* registers and the EL1, EL2, and EL3 ICC_* registers is enabled for EL3. '0' This register is always System register accessible. The GIC architecture permits, but does not require, that registers can be shared between memory-mapped registers and the equivalent System registers. This means that if the memory-mapped registers have been accessed while ICC_MSRE.SRE==0, then the System registers might be modified. Therefore, software must only rely on the reset values of the System registers if there has been no use of the GIC functionality while the memory-mapped registers are in use. Otherwise, the System register values must be treated as UNKNOWN. This register is only accessible when executing in Monitor mode. MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>} if !(IsFeatureImplemented(FEAT_AA32EL3) && IsFeatureImplemented(FEAT_GICv3) && HaveEL(EL3)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T12 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T12 == '1' then AArch32_TakeHypTrapException(0x03); else Undefined(); end; elsif PSTATE.EL == EL2 then Undefined(); elsif PSTATE.EL == EL3 then R(t) = ICC_MSRE(); end; MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>} if !(IsFeatureImplemented(FEAT_AA32EL3) && IsFeatureImplemented(FEAT_GICv3) && HaveEL(EL3)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T12 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T12 == '1' then AArch32_TakeHypTrapException(0x03); else Undefined(); end; elsif PSTATE.EL == EL2 then Undefined(); elsif PSTATE.EL == EL3 then if CP15SDISABLE2 == HIGH then Undefined(); else ICC_MSRE() = R(t); end; end; 2026-03-26 20:27:25 2026-03_rel