ICC_PMR
Interrupt Controller Interrupt Priority Mask Register
when FEAT_AA32EL1 is implemented and GICv3 is implemented
ICC_PMR_EL1
Architectural
AArch64
31
0
31
0
31
0
31
0
Provides an interrupt priority filter. Only interrupts with a higher priority than the value in this register are signaled to the PE.
GIC control registers
GIC
The effect of writes to ICC_PMR are guaranteed to be visible to later instructions in the Execution stream. This ensures that no interrupts below the written PMR value will be taken after a write to this register is architecturally executed. For more information, see 'Observability of the effects of accesses to the GIC registers' in ARM® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0 (ARM IHI 0069).
ICC_PMR is a 32-bit register.
31
8
31:8
Reserved, RES0.
Priority
7
0
7:0
The priority mask level for the CPU interface. If the priority of an interrupt is higher than the value indicated by this field, the interface signals the interrupt to the PE.
The possible priority field values are as follows:
Implemented priority bitsPossible priority field valuesNumber of priority levels
[7:0]0x00-0xFF (0-255), all values256
[7:1]0x00-0xFE (0-254), even values only128
[7:2]0x00-0xFC (0-252), in steps of 464
[7:3]0x00-0xF8 (0-248), in steps of 832
[7:4]0x00-0xF0 (0-240), in steps of 1616
Unimplemented priority bits are RAZ/WI.
0x00
MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
if !(IsFeatureImplemented(FEAT_AA32EL1) && IsFeatureImplemented(FEAT_GICv3)) then
Undefined();
elsif PSTATE.EL == EL0 then
Undefined();
elsif PSTATE.EL == EL1 then
if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && SCR_EL3().[IRQ,FIQ] == '11' then
Undefined();
elsif HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) && PSTATE.M != M32_Monitor && SCR().[IRQ,FIQ] == '11' then
Undefined();
elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T12 == '1' then
AArch64_AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T12 == '1' then
AArch32_TakeHypTrapException(0x03);
elsif ICC_SRE().SRE == '0' then
Undefined();
elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && ICH_HCR_EL2().TC == '1' then
AArch64_AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && ICH_HCR().TC == '1' then
AArch32_TakeHypTrapException(0x03);
elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HCR_EL2().FMO == '1' then
R(t) = ICV_PMR();
elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HCR_EL2().IMO == '1' then
R(t) = ICV_PMR();
elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HCR().FMO == '1' then
R(t) = ICV_PMR();
elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HCR().IMO == '1' then
R(t) = ICV_PMR();
elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && SCR_EL3().[IRQ,FIQ] == '11' then
if EL3SDDUndef() then
Undefined();
else
AArch64_AArch32SystemAccessTrap(EL3, 0x03);
end;
elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) && PSTATE.M != M32_Monitor && SCR().[IRQ,FIQ] == '11' then
if EL3SDDUndef() then
Undefined();
else
AArch32_TakeMonitorTrapException();
end;
else
R(t) = ICC_PMR();
end;
elsif PSTATE.EL == EL2 then
if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && SCR_EL3().[IRQ,FIQ] == '11' then
Undefined();
elsif HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) && SCR().[IRQ,FIQ] == '11' then
Undefined();
elsif ICC_HSRE().SRE == '0' then
Undefined();
elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && SCR_EL3().[IRQ,FIQ] == '11' then
if EL3SDDUndef() then
Undefined();
else
AArch64_AArch32SystemAccessTrap(EL3, 0x03);
end;
elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) && SCR().[IRQ,FIQ] == '11' then
if EL3SDDUndef() then
Undefined();
else
AArch32_TakeMonitorTrapException();
end;
else
R(t) = ICC_PMR();
end;
elsif PSTATE.EL == EL3 then
if ICC_MSRE().SRE == '0' then
Undefined();
else
R(t) = ICC_PMR();
end;
end;
MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
if !(IsFeatureImplemented(FEAT_AA32EL1) && IsFeatureImplemented(FEAT_GICv3)) then
Undefined();
elsif PSTATE.EL == EL0 then
Undefined();
elsif PSTATE.EL == EL1 then
if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && SCR_EL3().[IRQ,FIQ] == '11' then
Undefined();
elsif HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) && PSTATE.M != M32_Monitor && SCR().[IRQ,FIQ] == '11' then
Undefined();
elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T12 == '1' then
AArch64_AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T12 == '1' then
AArch32_TakeHypTrapException(0x03);
elsif ICC_SRE().SRE == '0' then
Undefined();
elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && ICH_HCR_EL2().TC == '1' then
AArch64_AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && ICH_HCR().TC == '1' then
AArch32_TakeHypTrapException(0x03);
elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HCR_EL2().FMO == '1' then
ICV_PMR() = R(t);
elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HCR_EL2().IMO == '1' then
ICV_PMR() = R(t);
elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HCR().FMO == '1' then
ICV_PMR() = R(t);
elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HCR().IMO == '1' then
ICV_PMR() = R(t);
elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && SCR_EL3().[IRQ,FIQ] == '11' then
if EL3SDDUndef() then
Undefined();
else
AArch64_AArch32SystemAccessTrap(EL3, 0x03);
end;
elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) && PSTATE.M != M32_Monitor && SCR().[IRQ,FIQ] == '11' then
if EL3SDDUndef() then
Undefined();
else
AArch32_TakeMonitorTrapException();
end;
else
ICC_PMR() = R(t);
end;
elsif PSTATE.EL == EL2 then
if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && SCR_EL3().[IRQ,FIQ] == '11' then
Undefined();
elsif HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) && SCR().[IRQ,FIQ] == '11' then
Undefined();
elsif ICC_HSRE().SRE == '0' then
Undefined();
elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && SCR_EL3().[IRQ,FIQ] == '11' then
if EL3SDDUndef() then
Undefined();
else
AArch64_AArch32SystemAccessTrap(EL3, 0x03);
end;
elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) && SCR().[IRQ,FIQ] == '11' then
if EL3SDDUndef() then
Undefined();
else
AArch32_TakeMonitorTrapException();
end;
else
ICC_PMR() = R(t);
end;
elsif PSTATE.EL == EL3 then
if ICC_MSRE().SRE == '0' then
Undefined();
else
ICC_PMR() = R(t);
end;
end;
2026-03-26 20:27:25
2026-03_rel