ICC_SRE Interrupt Controller System Register Enable register when FEAT_AA32EL1 is implemented and GICv3 is implemented ICC_SRE_EL1 Architectural AArch64 31 0 ICC_SRE_S 31 0 ICC_SRE_EL1_S 31 0 31 0 ICC_SRE_EL1 Architectural AArch64 31 0 ICC_SRE_NS 31 0 ICC_SRE_EL1_NS 31 0 31 0 ICC_SRE_EL1 Architectural AArch64 31 0 31 0 Controls whether the System register interface or the memory-mapped interface to the GIC CPU interface is used for EL0 and EL1. GIC control registers GIC This register is banked between ICC_SRE and ICC_SRE_S and ICC_SRE_NS. ICC_SRE is a 32-bit register. This register has the following instances: ICC_SRE, when EL3 is not implemented or FEAT_AA64 is implemented. ICC_SRE_S, when FEAT_AA32EL3 is implemented. ICC_SRE_NS, when FEAT_AA32EL3 is implemented. 31 3 31:3 Reserved, RES0. DIB 2 2 2 Disable IRQ bypass. If EL3 is implemented and GICD_CTLR.DS == 0, this field is a read-only alias of ICC_MSRE.DIB. If EL3 is implemented and GICD_CTLR.DS == 1, and EL2 is not implemented, this field is a read/write alias of ICC_MSRE.DIB. If EL3 is not implemented and EL2 is implemented, this field is a read-only alias of ICC_HSRE.DIB. If GICD_CTLR.DS == 1 and EL2 is implemented, this field is a read-only alias of ICC_HSRE.DIB. In systems that do not support IRQ bypass, this field is RAO/WI. 0b0 IRQ bypass enabled. 0b1 IRQ bypass disabled. '0' DFB 1 1 1 Disable FIQ bypass. If EL3 is implemented and GICD_CTLR.DS == 0, this field is a read-only alias of ICC_MSRE.DFB. If EL3 is implemented and GICD_CTLR.DS == 1, and EL2 is not implemented, this field is a read/write alias of ICC_MSRE.DFB. If EL3 is not implemented and EL2 is implemented, this field is a read-only alias of ICC_HSRE.DFB. If GICD_CTLR.DS == 1 and EL2 is implemented, this field is a read-only alias of ICC_HSRE.DFB. In systems that do not support FIQ bypass, this field is RAO/WI. 0b0 FIQ bypass enabled. 0b1 FIQ bypass disabled. '0' SRE 0 0 0 System Register Enable. If software changes this bit from 1 to 0 in the Secure instance of this register, the results are UNPREDICTABLE. If an implementation supports only a System register interface to the GIC CPU interface, this bit is RAO/WI. If EL3 is implemented and using AArch64: When ICC_SRE_EL3.SRE==0 the Secure copy of this bit is RAZ/WI. When ICC_SRE_EL3.SRE==0 the Non-secure copy of this bit is RAZ/WI. If EL3 is implemented and using AArch32: When ICC_MSRE.SRE==0 the Secure copy of this bit is RAZ/WI. When ICC_MSRE.SRE==0 the Non-secure copy of this bit is RAZ/WI. If EL2 is implemented and using AArch64: When ICC_SRE_EL2.SRE==0 the Non-secure copy of this bit is RAZ/WI. If EL2 is implemented and using AArch32: When ICC_HSRE.SRE==0 the Non-secure copy of this bit is RAZ/WI. 0b0 The memory-mapped interface must be used. Accesses at EL1 to any ICC_* System register other than ICC_SRE are UNDEFINED. 0b1 The System register interface for the current Security state is enabled. '0' The GIC architecture permits, but does not require, that registers can be shared between memory-mapped registers and the equivalent System registers. This means that if the memory-mapped registers have been accessed while ICC_SRE.SRE==0, then the System registers might be modified. Therefore, software must only rely on the reset values of the System registers if there has been no use of the GIC functionality while the memory-mapped registers are in use. Otherwise, the System register values must be treated as UNKNOWN. MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>} if !(IsFeatureImplemented(FEAT_AA32EL1) && IsFeatureImplemented(FEAT_GICv3)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && ICC_SRE_EL3().Enable == '0' then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T12 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T12 == '1' then AArch32_TakeHypTrapException(0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && EffectiveICC_SRE_EL2_Enable() == '0' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && ICC_HSRE().Enable == '0' then AArch32_TakeHypTrapException(0x03); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) && ICC_MSRE().Enable == '0' then Undefined(); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && ICC_SRE_EL3().Enable == '0' then if EL3SDDUndef() then Undefined(); else AArch64_AArch32SystemAccessTrap(EL3, 0x03); end; elsif HaveEL(EL3) then if EffectiveSCR_EL3_NS() == '0' then R(t) = ICC_SRE_S(); else R(t) = ICC_SRE_NS(); end; else R(t) = ICC_SRE(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && ICC_SRE_EL3().Enable == '0' then Undefined(); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && ICC_SRE_EL3().Enable == '0' then if EL3SDDUndef() then Undefined(); else AArch64_AArch32SystemAccessTrap(EL3, 0x03); end; elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) && ICC_MSRE().Enable == '0' then Undefined(); elsif HaveEL(EL3) then if EffectiveSCR_EL3_NS() == '0' then R(t) = ICC_SRE_S(); else R(t) = ICC_SRE_NS(); end; else R(t) = ICC_SRE(); end; elsif PSTATE.EL == EL3 then if EffectiveSCR_EL3_NS() == '0' then R(t) = ICC_SRE_S(); else R(t) = ICC_SRE_NS(); end; end; MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>} if !(IsFeatureImplemented(FEAT_AA32EL1) && IsFeatureImplemented(FEAT_GICv3)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && ICC_SRE_EL3().Enable == '0' then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T12 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T12 == '1' then AArch32_TakeHypTrapException(0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && EffectiveICC_SRE_EL2_Enable() == '0' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && ICC_HSRE().Enable == '0' then AArch32_TakeHypTrapException(0x03); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) && ICC_MSRE().Enable == '0' then Undefined(); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && ICC_SRE_EL3().Enable == '0' then if EL3SDDUndef() then Undefined(); else AArch64_AArch32SystemAccessTrap(EL3, 0x03); end; elsif HaveEL(EL3) then if EffectiveSCR_EL3_NS() == '0' then ICC_SRE_S() = R(t); else ICC_SRE_NS() = R(t); end; else ICC_SRE() = R(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && ICC_SRE_EL3().Enable == '0' then Undefined(); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && ICC_SRE_EL3().Enable == '0' then if EL3SDDUndef() then Undefined(); else AArch64_AArch32SystemAccessTrap(EL3, 0x03); end; elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) && ICC_MSRE().Enable == '0' then Undefined(); elsif HaveEL(EL3) then if EffectiveSCR_EL3_NS() == '0' then ICC_SRE_S() = R(t); else ICC_SRE_NS() = R(t); end; else ICC_SRE() = R(t); end; elsif PSTATE.EL == EL3 then if EffectiveSCR_EL3_NS() == '0' then ICC_SRE_S() = R(t); else ICC_SRE_NS() = R(t); end; end; 2026-03-26 20:27:25 2026-03_rel