ICH_AP0R<n> Interrupt Controller Hyp Active Priorities Group 0 Registers when FEAT_AA32EL2 is implemented, GICv3 is implemented, and (EL2 is implemented or EL3 is implemented) 0 3 ICH_AP0R<n>_EL2 Architectural AArch64 31 0 31 0 31 0 31 0 Provides information about Group 0 active priorities for EL2. GIC GIC Host Interface Control Registers Virt If EL2 is not implemented, this register is RES0 from EL3. ICH_AP0R<n> is a 32-bit register. P<x> 31 0 31:0 Provides the access to the virtual active priorities for Group 0 interrupts. Possible values of each bit are: The correspondence between priority levels and bits depends on the number of bits of priority that are implemented. If 5 bits of preemption are implemented (bits [7:3] of priority), then there are 32 preemption levels, and the active state of these preemption levels are held in ICH_AP0R0 in the bits corresponding to Priority[7:3]. If 6 bits of preemption are implemented (bits [7:2] of priority), then there are 64 preemption levels, and: The active state of preemption levels 0 - 124 are held in ICH_AP0R0 in the bits corresponding to 0:Priority[6:2]. The active state of preemption levels 128 - 252 are held in ICH_AP0R1 in the bits corresponding to 1:Priority[6:2]. If 7 bits of preemption are implemented (bits [7:1] of priority), then there are 128 preemption levels, and: The active state of preemption levels 0 - 62 are held in ICH_AP0R0 in the bits corresponding to 00:Priority[5:1]. The active state of preemption levels 64 - 126 are held in ICH_AP0R1 in the bits corresponding to 01:Priority[5:1]. The active state of preemption levels 128 - 190 are held in ICH_AP0R2 in the bits corresponding to 10:Priority[5:1]. The active state of preemption levels 192 - 254 are held in ICH_AP0R3 in the bits corresponding to 11:Priority[5:1]. Having the bit corresponding to a priority set to 1 in both ICH_AP0R<n> and ICH_AP1R<n> might result in UNPREDICTABLE behavior of the interrupt prioritization system for virtual interrupts. 31 0 0b0 There is no Group 0 interrupt active at the priority corresponding to that bit. 0b1 There is a Group 0 interrupt active at the priority corresponding to that bit. 0x00000000 ICH_AP0R1 is implemented only in implementations that support 6 or more bits of preemption. ICH_AP0R2 and ICH_AP0R3 are implemented only in implementations that support 7 bits of preemption. Unimplemented registers are UNDEFINED. The number of bits of preemption is indicated by ICH_VTR.PREbits Writing to the active priority registers in any order other than the following order will result in UNPREDICTABLE behavior: ICH_AP0R<n> ICH_AP1R<n> 0-3 MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>} let m:integer = UInt(opc2[1:0]); if !(IsFeatureImplemented(FEAT_AA32EL2) && IsFeatureImplemented(FEAT_GICv3) && (HaveEL(EL2) || HaveEL(EL3))) then Undefined(); elsif m == 1 && NUM_GIC_PREEMPTION_BITS < 6 then Undefined(); elsif (m == 2 || m == 3) && NUM_GIC_PREEMPTION_BITS < 7 then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T12 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T12 == '1' then AArch32_TakeHypTrapException(0x03); else Undefined(); end; elsif PSTATE.EL == EL2 then if ICC_HSRE().SRE == '0' then Undefined(); else R(t) = ICH_AP0R(m); end; elsif PSTATE.EL == EL3 then if ICC_MSRE().SRE == '0' then Undefined(); else R(t) = ICH_AP0R(m); end; end; 0-3 MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>} let m:integer = UInt(opc2[1:0]); if !(IsFeatureImplemented(FEAT_AA32EL2) && IsFeatureImplemented(FEAT_GICv3) && (HaveEL(EL2) || HaveEL(EL3))) then Undefined(); elsif m == 1 && NUM_GIC_PREEMPTION_BITS < 6 then Undefined(); elsif (m == 2 || m == 3) && NUM_GIC_PREEMPTION_BITS < 7 then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T12 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T12 == '1' then AArch32_TakeHypTrapException(0x03); else Undefined(); end; elsif PSTATE.EL == EL2 then if ICC_HSRE().SRE == '0' then Undefined(); else ICH_AP0R(m) = R(t); end; elsif PSTATE.EL == EL3 then if ICC_MSRE().SRE == '0' then Undefined(); else ICH_AP0R(m) = R(t); end; end; 2026-03-26 20:27:25 2026-03_rel