ICH_EISR Interrupt Controller End of Interrupt Status Register when FEAT_AA32EL2 is implemented, GICv3 is implemented, and (EL2 is implemented or EL3 is implemented) ICH_EISR_EL2 Architectural AArch64 31 0 31 0 31 0 31 0 Indicates which List registers have outstanding EOI maintenance interrupts. GIC GIC Host Interface Control Registers Virt If EL2 is not implemented, this register is RES0 from EL3. ICH_EISR is a 32-bit register. 31 16 31:16 Reserved, RES0. Status<n> 15 0 15:0 EOI maintenance interrupt status bit for List register <n>: For any ICH_LR<n>, the corresponding status bit is set to 1 if all of the following are true: ICH_LRC<n>.State is 0b00. ICH_LRC<n>.HW is 0. ICH_LRC<n>.EOI (bit [9]) is 1, indicating that when the interrupt corresponding to that List register is deactivated, a maintenance interrupt is asserted. 15 0 0b0 List register <n>, ICH_LR<n>, does not have an EOI maintenance interrupt. 0b1 List register <n>, ICH_LR<n>, has an EOI maintenance interrupt that has not been handled. 0x0000 MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>} if !(IsFeatureImplemented(FEAT_AA32EL2) && IsFeatureImplemented(FEAT_GICv3) && (HaveEL(EL2) || HaveEL(EL3))) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T12 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T12 == '1' then AArch32_TakeHypTrapException(0x03); else Undefined(); end; elsif PSTATE.EL == EL2 then if ICC_HSRE().SRE == '0' then Undefined(); else R(t) = ICH_EISR(); end; elsif PSTATE.EL == EL3 then if ICC_MSRE().SRE == '0' then Undefined(); else R(t) = ICH_EISR(); end; end; 2026-03-26 20:27:25 2026-03_rel