ICH_HCR Interrupt Controller Hyp Control Register when FEAT_AA32EL2 is implemented, GICv3 is implemented, and (EL2 is implemented or EL3 is implemented) ICH_HCR_EL2 Architectural AArch64 31 0 31 0 31 0 31 0 Controls the environment for VMs. GIC GIC Host Interface Control Registers Virt If EL2 is not implemented, this register is RES0 from EL3. ICH_HCR is a 32-bit register. EOIcount 31 27 31:27 This field is incremented whenever a successful write to a virtual EOIR or DIR register would have resulted in a virtual interrupt deactivation. That is either: A virtual write to EOIR with a valid interrupt identifier that is not in the LPI range (that is < 8192) when EOI mode is zero and no List Register was found. A virtual write to DIR with a valid interrupt identifier that is not in the LPI range (that is < 8192) when EOI mode is one and no List Register was found. This allows software to manage more active interrupts than there are implemented List Registers. It is CONSTRAINED UNPREDICTABLE whether a virtual write to EOIR that does not clear a bit in the Active Priorities registers (ICH_AP0R<n>/ICH_AP1R<n>) increments EOIcount. Permitted behaviors are: Increment EOIcount. Leave EOIcount unchanged. '00000' 26 15 26:15 Reserved, RES0. TDIR 14 14 0 Trap Non-secure EL1 writes to ICC_DIR and ICV_DIR. Arm deprecates not including this trap bit. 0b0 Non-secure EL1 writes of ICC_DIR and ICV_DIR are not trapped to EL2, unless trapped by other mechanisms. 0b1 Non-secure EL1 writes of ICV_DIR are trapped to EL2. It is IMPLEMENTATION DEFINED whether Non-secure writes of ICC_DIR are trapped. Not trapping ICC_DIR writes is DEPRECATED. '0' When FEAT_GICv3_TDIR is implemented 14 14 14 Reserved, RES0. Otherwise TSEI 13 13 13 Trap all locally generated SEIs. This bit allows the hypervisor to intercept locally generated SEIs that would otherwise be taken at Non-secure EL1. If ICH_VTR.SEIS is 0, this bit is RES0. 0b0 Locally generated SEIs do not cause a trap to EL2. 0b1 Locally generated SEIs trap to EL2. '0' TALL1 12 12 12 Trap all Non-secure EL1 accesses to ICC_* and ICV_* System registers for Group 1 interrupts to EL2. 0b0 Non-secure EL1 accesses to ICC_* and ICV_* registers for Group 1 interrupts proceed as normal. 0b1 Non-secure EL1 accesses to ICC_* and ICV_* registers for Group 1 interrupts trap to EL2. '0' TALL0 11 11 11 Trap all Non-secure EL1 accesses to ICC_* and ICV_* System registers for Group 0 interrupts to EL2. 0b0 Non-secure EL1 accesses to ICC_* and ICV_* registers for Group 0 interrupts proceed as normal. 0b1 Non-secure EL1 accesses to ICC_* and ICV_* registers for Group 0 interrupts trap to EL2. '0' TC 10 10 10 Trap all Non-secure EL1 accesses to System registers that are common to Group 0 and Group 1 to EL2. This affects accesses to ICC_SGI0R, ICC_SGI1R, ICC_ASGI1R, ICC_CTLR, ICC_DIR, ICC_PMR, ICC_RPR, ICV_CTLR, ICV_DIR, ICV_PMR, and ICV_RPR. 0b0 Non-secure EL1 accesses to common registers proceed as normal. 0b1 Non-secure EL1 accesses to common registers trap to EL2. '0' 9 9 9 Reserved, RES0. vSGIEOICount 8 8 0 Controls whether deactivation of virtual SGIs can increment ICH_HCR_EL2.EOIcount 0b0 Deactivation of virtual SGIs can increment ICH_HCR.EOIcount. 0b1 Deactivation of virtual SGIs does not increment ICH_HCR.EOIcount. '0' When GICv4.1 is implemented 8 8 8 Reserved, RES0. Otherwise VGrp1DIE 7 7 7 VM Group 1 Disabled Interrupt Enable. Enables the signaling of a maintenance interrupt while signaling of Group 1 interrupts from the virtual CPU interface to the connected vPE is disabled: 0b0 Maintenance interrupt disabled. 0b1 Maintenance interrupt signaled when ICH_VMCR.VENG1 is 0. '0' VGrp1EIE 6 6 6 VM Group 1 Enabled Interrupt Enable. Enables the signaling of a maintenance interrupt while signaling of Group 1 interrupts from the virtual CPU interface to the connected vPE is enabled: 0b0 Maintenance interrupt disabled. 0b1 Maintenance interrupt signaled when ICH_VMCR.VENG1 is 1. '0' VGrp0DIE 5 5 5 VM Group 0 Disabled Interrupt Enable. Enables the signaling of a maintenance interrupt while signaling of Group 0 interrupts from the virtual CPU interface to the connected vPE is disabled: 0b0 Maintenance interrupt disabled. 0b1 Maintenance interrupt signaled when ICH_VMCR.VENG0 is 0. '0' VGrp0EIE 4 4 4 VM Group 0 Enabled Interrupt Enable. Enables the signaling of a maintenance interrupt while signaling of Group 0 interrupts from the virtual CPU interface to the connected vPE is enabled: 0b0 Maintenance interrupt disabled. 0b1 Maintenance interrupt signaled when ICH_VMCR.VENG0 is 1. '0' NPIE 3 3 3 No Pending Interrupt Enable. Enables the signaling of a maintenance interrupt when there are no List registers with the State field set to 0b01 (pending): 0b0 Maintenance interrupt disabled. 0b1 Maintenance interrupt signaled while the List registers contain no interrupts in the pending state. '0' LRENPIE 2 2 2 List Register Entry Not Present Interrupt Enable. Enables the signaling of a maintenance interrupt while the virtual CPU interface does not have a corresponding valid List register entry for an EOI request: 0b0 Maintenance interrupt disabled. 0b1 Maintenance interrupt is asserted while the EOIcount field is not 0. '0' UIE 1 1 1 Underflow Interrupt Enable. Enables the signaling of a maintenance interrupt when the List registers are empty, or hold only one valid entry: 0b0 Maintenance interrupt disabled. 0b1 Maintenance interrupt is asserted if none, or only one, of the List register entries is marked as a valid interrupt. '0' En 0 0 0 Enable. Global enable bit for the virtual CPU interface: When this field is set to 0: The virtual CPU interface does not signal any maintenance interrupts. The virtual CPU interface does not signal any virtual interrupts. A read of ICV_IAR0, ICV_IAR1, GICV_IAR or GICV_AIAR returns a spurious interrupt ID. 0b0 Virtual CPU interface operation disabled. 0b1 Virtual CPU interface operation enabled. '0' MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>} if !(IsFeatureImplemented(FEAT_AA32EL2) && IsFeatureImplemented(FEAT_GICv3) && (HaveEL(EL2) || HaveEL(EL3))) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T12 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T12 == '1' then AArch32_TakeHypTrapException(0x03); else Undefined(); end; elsif PSTATE.EL == EL2 then if ICC_HSRE().SRE == '0' then Undefined(); else R(t) = ICH_HCR(); end; elsif PSTATE.EL == EL3 then if ICC_MSRE().SRE == '0' then Undefined(); else R(t) = ICH_HCR(); end; end; MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>} if !(IsFeatureImplemented(FEAT_AA32EL2) && IsFeatureImplemented(FEAT_GICv3) && (HaveEL(EL2) || HaveEL(EL3))) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T12 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T12 == '1' then AArch32_TakeHypTrapException(0x03); else Undefined(); end; elsif PSTATE.EL == EL2 then if ICC_HSRE().SRE == '0' then Undefined(); else ICH_HCR() = R(t); end; elsif PSTATE.EL == EL3 then if ICC_MSRE().SRE == '0' then Undefined(); else ICH_HCR() = R(t); end; end; 2026-03-26 20:27:25 2026-03_rel